Joachim Strömbergson 00599549e3 FPGA: Add system reset API ... Add API address to trigger system reset. When written to will send system_reset signal to the reset generator, which then perform a complete reset cycle of the FPGA system. Signed-off-by: Joachim Strömbergson <joachim@assured.se>		2024-08-20 13:25:22 +02:00
..
picorv32	FPGA: Ignore warnings about blocking assignment in clocked processes	2024-06-17 15:37:13 +02:00
timer	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
tk1	FPGA: Add system reset API	2024-08-20 13:25:22 +02:00
touch_sense	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
trng	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
uart	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
uds	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00