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3cf218469c
Describe how the UDI and UDS are actually stored in the FPGA, how they are accessed, and how they are initialled by the patch_uds_udi.py script. Co-authored-by: Joachim Strömbergson <joachim@assured.se>
90 lines
2.9 KiB
Python
90 lines
2.9 KiB
Python
# -*- coding: utf-8 -*-
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#=======================================================================
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#
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# Copyright (C) 2023 Tillitis AB
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# Written by Myrtle Shah <gatecat@ds0.me>
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# SPDX-License-Identifier: GPL-2.0-only
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#
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# Script to patch in a Unique Device Secret (UDS) and a Unique Device
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# Identifier (UDI) from files into a bitstream.
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#
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# It's supposed to be run like this:
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#
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# nextpnr-ice40 --up5k --package sg48 --ignore-loops \
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# --json application_fpga_par.json --run patch_uds_udi.py
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#
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# with this environment:
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#
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# - UDS_HEX: path to the UDS file, typically the path to
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# ../data/uds.hex
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# - UDI_HEX: path to the UDI file, typically the path to ../data/udi.hex
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# - OUT_ASC: path to the ASC output that is then used by icebram and icepack.
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#
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# The script changes the UDS and UDI that are stored in named 4-bit
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# LUT instances in the JSON file so we can generate device
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# unique bitstreams without running the complete flow just to change
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# UDS and UDI. Then we can just run the final bitstream generation
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# from the ASC file.
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#
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# We represent our UDI and UDS values as a number of 32 bit words:
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#
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# - UDI: 2 words.
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# - UDS: 8 words.
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#
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# We reserve 32 named 4-bit LUTs *each* to store the data: UDS in
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# "uds_rom_idx" and UDI in "udi_rom_idx".
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#
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# The script repeats the value in the LUTs so we don't have to care
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# about the value of the unused address bits.
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#
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# See documentation in their implementation in ../core/uds/README.md
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# and ../core/tk1/README.md
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import os
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def parse_hex(file, length):
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data = []
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with open(file, "r") as f:
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for line in f:
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l = line.strip()
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if len(l) > 0:
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data.append(int(l, 16))
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assert len(data) == length, len(data)
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return data
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def rewrite_lut(lut, idx, data, has_re=False):
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# each LUT provides one bit per 32-bit word out of 64/256 bits total
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new_init = 0
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for i, word in enumerate(data):
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if (word >> idx) & 0x1:
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# repeat so we don't have to care about inputs above
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# address
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repeat = (16 // len(data))
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for k in range(repeat):
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# UDS also has a read enable
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# LUT output is zero if this isn't asserted
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if has_re and k < (repeat // 2):
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continue
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new_init |= (1 << (k * len(data) + i))
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lut.setParam("LUT_INIT", f"{new_init:016b}")
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uds = parse_hex(os.environ["UDS_HEX"], 8)
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udi = parse_hex(os.environ["UDI_HEX"], 2)
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uds_lut_count = 0
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udi_lut_count = 0
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for cell_name, cell in ctx.cells:
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if "uds_rom_idx" in cell.attrs:
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index = int(cell.attrs["uds_rom_idx"], 2)
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rewrite_lut(cell, index, uds, True)
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uds_lut_count += 1
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if "udi_rom_idx" in cell.attrs:
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index = int(cell.attrs["udi_rom_idx"], 2)
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rewrite_lut(cell, index, udi, False)
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udi_lut_count += 1
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assert uds_lut_count == 32, uds_lut_count
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assert udi_lut_count == 32, udi_lut_count
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write_bitstream(ctx, os.environ["OUT_ASC"])
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