35052e50cb
Move the logic implementing the RAM address and data
scrambling, descrambling into the RAM module. This cleans up
the top level, and makes it easier to change the scrambling
without chaning the top. In order to do correct scrambling the
address to the RAM core must be 16 bits, not 15.
Clean up some minor details at the top level, fixing text
aligment and grouping of ports in instances.
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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| README.md | ||
ram
RAM for the application.
Introduction
This core implements the 128 kByte RAM available for the device applications. The core also implements (from the view of the CPU) transparent RAM address and data scrambling. This scrambling is applied to make it harder to extract application and application data from a memory dump directly from the memory cores.
API
The core does not have an API.
Implementation Details
The core is implemented by explicitly instantiating the four SB_SPRAM256KA 16 kW16 cores in the FPGA. The blocks are used in pairs to achieve a complete 32kW32 RAM.
The RAM address and data scrambling use 32 bit ram_addr_rand and ram_data_rand inputs as seeds for the scrambling mechanism. When data is read out it is descrambled before sent out on the read_data output port. The scrambling functionality does not add latency.
Note: the scrambling mechanism is NOT a cryptographically secure function. Even if it was, a 32 bit key would be too short to add any security.