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fix_flash_make_target
tillitis-key/hw/application_fpga
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Joachim Strömbergson 35052e50cb
FPGA: Move RAM address and data scrambling into the RAM module. 
Move the logic implementing the RAM address and data
	scrambling, descrambling into the RAM module. This cleans up
	the top level, and makes it easier to change the scrambling
	without chaning the top. In order to do correct scrambling the
	address to the RAM core must be 16 bits, not 15.

	Clean up some minor details at the top level, fixing text
        aligment and grouping of ports in instances.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-08-30 10:53:13 +02:00
..
core FPGA: Move RAM address and data scrambling into the RAM module. 2024-08-30 10:53:13 +02:00
data A construction of a minimal SPI master. 2024-06-11 15:28:29 +02:00
fw FPGA: Add system reset API 2024-08-20 13:25:22 +02:00
rtl FPGA: Move RAM address and data scrambling into the RAM module. 2024-08-30 10:53:13 +02:00
tb Rename to TK1 2022-10-26 09:20:02 +02:00
tools hw/tool: UDI/UDS storage 2024-04-03 11:27:00 +02:00
application_fpga.bin.sha256 FPGA: Move RAM address and data scrambling into the RAM module. 2024-08-30 10:53:13 +02:00
config.vlt Config verilator lint to ignore known 3rd-party warnings; let warnings be fatal 2023-03-01 13:37:31 +01:00
firmware.bin.sha512 FPGA: Move RAM address and data scrambling into the RAM module. 2024-08-30 10:53:13 +02:00
Makefile FPGA: Move all sub modules into separate cores 2024-08-29 16:06:58 +02:00