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tillitis-key/hw/application_fpga/data
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Exact
Jonas Thörnblad 48cbb55d6e
Add incoming and outgoing CTS (Clear To Send) signals for the FPGA 
to let the CH552 and FPGA signal each other that it is OK to send
UART data. The CTS signals indicate "OK to send" if high. If an
incoming CTS signal goes low, the receiver of that signal should
immediatly stop sending UART data.
2024-12-17 17:18:45 +01:00
..
application_fpga_mta1_usb_dev.pcf Rename to TK1 2022-10-26 09:20:02 +02:00
application_fpga_tk1.pcf Add incoming and outgoing CTS (Clear To Send) signals for the FPGA 2024-12-17 17:18:45 +01:00
udi.hex Make initial public release 2022-09-19 08:51:11 +02:00
uds.hex Use different byte values in test UDS words 2023-03-28 09:26:23 +02:00