mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2025-03-12 10:06:47 -04:00
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37
.github/workflows/ci.yaml
vendored
37
.github/workflows/ci.yaml
vendored
@ -10,31 +10,10 @@ on:
|
||||
workflow_dispatch: {}
|
||||
|
||||
jobs:
|
||||
check-formatting:
|
||||
runs-on: ubuntu-latest
|
||||
container:
|
||||
image: ghcr.io/tillitis/tkey-builder:5rc1
|
||||
steps:
|
||||
- name: checkout
|
||||
uses: actions/checkout@v4
|
||||
with:
|
||||
# fetch-depth: 0
|
||||
persist-credentials: false
|
||||
|
||||
- name: fix
|
||||
# https://github.com/actions/runner-images/issues/6775
|
||||
run: |
|
||||
git config --global --add safe.directory "$GITHUB_WORKSPACE"
|
||||
|
||||
- name: check formatting on Verilog and C
|
||||
working-directory: hw/application_fpga
|
||||
run: |
|
||||
make checkfmt
|
||||
|
||||
check-firmware:
|
||||
runs-on: ubuntu-latest
|
||||
container:
|
||||
image: ghcr.io/tillitis/tkey-builder:5rc1
|
||||
image: ghcr.io/tillitis/tkey-builder:4
|
||||
steps:
|
||||
- name: checkout
|
||||
uses: actions/checkout@v4
|
||||
@ -47,6 +26,12 @@ jobs:
|
||||
run: |
|
||||
git config --global --add safe.directory "$GITHUB_WORKSPACE"
|
||||
|
||||
- name: check indentation in firmware C code
|
||||
working-directory: hw/application_fpga
|
||||
run: |
|
||||
make -C fw/tk1 checkfmt
|
||||
make -C fw/testfw checkfmt
|
||||
|
||||
- name: run static analysis on firmware C code
|
||||
working-directory: hw/application_fpga
|
||||
run: |
|
||||
@ -59,7 +44,7 @@ jobs:
|
||||
check-verilog:
|
||||
runs-on: ubuntu-latest
|
||||
container:
|
||||
image: ghcr.io/tillitis/tkey-builder:5rc1
|
||||
image: ghcr.io/tillitis/tkey-builder:4
|
||||
steps:
|
||||
- name: checkout
|
||||
uses: actions/checkout@v4
|
||||
@ -79,7 +64,7 @@ jobs:
|
||||
build-usb-firmware:
|
||||
runs-on: ubuntu-latest
|
||||
container:
|
||||
image: ghcr.io/tillitis/tkey-builder:5rc1
|
||||
image: ghcr.io/tillitis/tkey-builder:4
|
||||
steps:
|
||||
- name: checkout
|
||||
uses: actions/checkout@v4
|
||||
@ -101,7 +86,7 @@ jobs:
|
||||
commit_sha: ${{ github.sha }}
|
||||
runs-on: ubuntu-latest
|
||||
container:
|
||||
image: ghcr.io/tillitis/tkey-builder:5rc1
|
||||
image: ghcr.io/tillitis/tkey-builder:4
|
||||
steps:
|
||||
- name: checkout
|
||||
uses: actions/checkout@v4
|
||||
@ -130,7 +115,7 @@ jobs:
|
||||
needs: build-bitstream
|
||||
runs-on: ubuntu-latest
|
||||
container:
|
||||
image: ghcr.io/tillitis/tkey-builder:5rc1
|
||||
image: ghcr.io/tillitis/tkey-builder:4
|
||||
steps:
|
||||
- name: Checkout
|
||||
uses: actions/checkout@v4
|
||||
|
||||
@ -12,7 +12,6 @@ RUN apt-get -qq update -y \
|
||||
clang-format \
|
||||
clang-tidy \
|
||||
cmake \
|
||||
curl \
|
||||
flex \
|
||||
g++ \
|
||||
gawk \
|
||||
@ -58,12 +57,109 @@ RUN apt-get -qq update -y \
|
||||
zlib1g-dev \
|
||||
&& rm -rf /var/lib/apt/lists/*
|
||||
|
||||
# Enable bash completion
|
||||
RUN sed -i '/#if ! shopt -oq posix; then/ s/^#//' /etc/bash.bashrc
|
||||
RUN sed -i '/# if \[ -f \/usr\/share\/bash-completion\/bash_completion \]; then/ s/^#//' /etc/bash.bashrc
|
||||
RUN sed -i '/# . \/usr\/share\/bash-completion\/bash_completion/ s/^#//' /etc/bash.bashrc
|
||||
RUN sed -i '/# elif \[ -f \/etc\/bash_completion \]; then/ s/^#//' /etc/bash.bashrc
|
||||
RUN sed -i '/# . \/etc\/bash_completion/ s/^#//' /etc/bash.bashrc
|
||||
RUN sed -i '/# fi/ s/^#//' /etc/bash.bashrc
|
||||
RUN sed -i '/#fi/ s/^#//' /etc/bash.bashrc
|
||||
|
||||
FROM base as toolsbuilder
|
||||
|
||||
COPY buildtools.sh /buildtools.sh
|
||||
COPY verible.sha512 /verible.sha512
|
||||
RUN git clone --depth=1 https://github.com/YosysHQ/icestorm /src
|
||||
WORKDIR /src
|
||||
RUN git checkout 738af822905fdcf0466e9dd784b9ae4b0b34987f \
|
||||
&& make -j$(nproc --ignore=2) \
|
||||
&& make install \
|
||||
&& git describe --all --always --long --dirty > /usr/local/repo-commit-icestorm
|
||||
WORKDIR /
|
||||
RUN rm -rf /src
|
||||
|
||||
RUN /buildtools.sh
|
||||
# Custom iceprog for the RPi 2040-based programmer (will be upstreamed).
|
||||
RUN git clone -b interfaces --depth=1 https://github.com/tillitis/icestorm /src
|
||||
WORKDIR /src/iceprog
|
||||
RUN make -j$(nproc --ignore=2) \
|
||||
&& make PROGRAM_PREFIX=tillitis- install \
|
||||
&& git describe --all --always --long --dirty > /usr/local/repo-commit-tillitis--icestorm
|
||||
WORKDIR /
|
||||
RUN rm -rf /src
|
||||
|
||||
RUN git clone -b 0.45 --depth=1 https://github.com/YosysHQ/yosys /src
|
||||
WORKDIR /src
|
||||
RUN git submodule update --init \
|
||||
&& make -j$(nproc --ignore=2) \
|
||||
&& make install \
|
||||
&& git describe --all --always --long --dirty > /usr/local/repo-commit-yosys
|
||||
WORKDIR /
|
||||
RUN rm -rf /src
|
||||
|
||||
RUN git clone -b nextpnr-0.7 https://github.com/YosysHQ/nextpnr /src
|
||||
WORKDIR /src
|
||||
# Add "Fix handling of RNG seed" #1369
|
||||
RUN git cherry-pick --no-commit 6ca64526bb18ace8690872b09ca1251567c116de
|
||||
# Add early exit if place fails on timing
|
||||
RUN sed -i \
|
||||
'345i \ \ \ \ general.add_options()("exit-on-failed-target-frequency",' \
|
||||
common/kernel/command.cc
|
||||
RUN sed -i \
|
||||
'346i \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ "exit if target frequency is not achieved (use together with "' \
|
||||
common/kernel/command.cc
|
||||
RUN sed -i \
|
||||
'347i \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ "--randomize-seed option)");' \
|
||||
common/kernel/command.cc
|
||||
RUN sed -i \
|
||||
'348i \\' \
|
||||
common/kernel/command.cc
|
||||
RUN sed -i \
|
||||
'662s/if (do_route) {/if (do_route \&\& (vm.count("exit-on-failed-target-frequency") ? !had_nonfatal_error : true)) {/' \
|
||||
common/kernel/command.cc
|
||||
RUN sed -i \
|
||||
'244s/bool warn_on_failure = false/bool warn_on_failure = true/' \
|
||||
common/kernel/timing.h
|
||||
RUN cmake -DARCH=ice40 . \
|
||||
&& make -j$(nproc --ignore=2) \
|
||||
&& make install \
|
||||
&& git describe --all --always --long --dirty > /usr/local/repo-commit-nextpnr
|
||||
WORKDIR /
|
||||
RUN rm -rf /src
|
||||
|
||||
RUN git clone -b v12_0 --depth=1 https://github.com/steveicarus/iverilog /src
|
||||
WORKDIR /src
|
||||
RUN sh autoconf.sh \
|
||||
&& ./configure \
|
||||
&& make -j$(nproc --ignore=2) \
|
||||
&& make install \
|
||||
&& git describe --all --always --long --dirty > /usr/local/repo-commit-iverilog
|
||||
WORKDIR /
|
||||
RUN rm -rf /src
|
||||
|
||||
RUN git clone -b v5.028 --depth=1 https://github.com/verilator/verilator /src
|
||||
WORKDIR /src
|
||||
RUN autoconf \
|
||||
&& ./configure \
|
||||
&& make -j$(nproc --ignore=2) \
|
||||
&& make test \
|
||||
&& make install \
|
||||
&& git describe --all --always --long --dirty > /usr/local/repo-commit-verilator
|
||||
WORKDIR /
|
||||
RUN rm -rf /src
|
||||
|
||||
ADD https://github.com/chipsalliance/verible/releases/download/v0.0-3795-gf4d72375/verible-v0.0-3795-gf4d72375-linux-static-x86_64.tar.gz /src/verible.tar.gz
|
||||
WORKDIR /src
|
||||
RUN tar xvf verible.tar.gz
|
||||
RUN mv -v verible*/bin/* /usr/local/bin
|
||||
RUN verible-verilog-format --version | head -1 > /usr/local/repo-commit-verible
|
||||
WORKDIR /
|
||||
RUN rm -rf /src
|
||||
|
||||
RUN git clone -b v1.9.1 https://github.com/cocotb/cocotb.git /src
|
||||
WORKDIR /src
|
||||
RUN pip install . --break-system-packages \
|
||||
&& git describe --all --always --long --dirty > /usr/local/repo-commit-cocotb
|
||||
WORKDIR /
|
||||
RUN rm -rf /src
|
||||
|
||||
FROM base
|
||||
LABEL org.opencontainers.image.description="Toolchain for building TKey FPGA bitstream"
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
BUILDIMAGE=tkey-builder-local
|
||||
|
||||
# default image used when running a container
|
||||
IMAGE=ghcr.io/tillitis/tkey-builder:5rc1
|
||||
IMAGE=ghcr.io/tillitis/tkey-builder:4
|
||||
|
||||
all:
|
||||
@echo "Targets:"
|
||||
@ -23,11 +23,11 @@ all:
|
||||
|
||||
run:
|
||||
podman run --rm --mount type=bind,source="`pwd`/../",target=/build -w /build -it \
|
||||
$(IMAGE) /usr/bin/bash -l
|
||||
$(IMAGE) /usr/bin/bash
|
||||
|
||||
docker-run:
|
||||
docker run --rm --mount type=bind,source="`pwd`/../",target=/build -w /build -it \
|
||||
$(IMAGE) /usr/bin/bash -l
|
||||
$(IMAGE) /usr/bin/bash
|
||||
|
||||
run-make:
|
||||
podman run --rm --mount type=bind,source="`pwd`/../hw/application_fpga",target=/build -w /build -it \
|
||||
|
||||
@ -1,134 +0,0 @@
|
||||
#! /bin/sh -e
|
||||
|
||||
# Copyright (C) 2025 Tillitis AB
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
## Build the specific versions of the tools we need to build the TKey
|
||||
## FPGA bitstream and apps.
|
||||
|
||||
cd /
|
||||
mkdir src
|
||||
|
||||
# ----------------------------------------------------------------------
|
||||
# Project icestorm
|
||||
# ----------------------------------------------------------------------
|
||||
git clone https://github.com/YosysHQ/icestorm /src/icestorm
|
||||
cd /src/icestorm
|
||||
|
||||
# No tags or releases yet. Pin down to a specific commit.
|
||||
git checkout 738af822905fdcf0466e9dd784b9ae4b0b34987f
|
||||
make -j$(nproc --ignore=2)
|
||||
make install
|
||||
git describe --all --always --long --dirty > /usr/local/repo-commit-icestorm
|
||||
|
||||
# ----------------------------------------------------------------------
|
||||
# Our own custom iceprog for the RPi 2040-based programmer. Will be
|
||||
# upstreamed.
|
||||
# ----------------------------------------------------------------------
|
||||
git clone -b interfaces --depth=1 https://github.com/tillitis/icestorm /src/icestorm-tillitis
|
||||
cd /src/icestorm-tillitis/iceprog
|
||||
make -j$(nproc --ignore=2)
|
||||
make PROGRAM_PREFIX=tillitis- install
|
||||
git describe --all --always --long --dirty > /usr/local/repo-commit-tillitis--icestorm
|
||||
|
||||
# ----------------------------------------------------------------------
|
||||
# yosys
|
||||
# ----------------------------------------------------------------------
|
||||
git clone -b 0.45 --depth=1 https://github.com/YosysHQ/yosys /src/yosys
|
||||
cd /src/yosys
|
||||
|
||||
# Make sure the digest is correct and no history has changed
|
||||
git checkout 9ed031ddd588442f22be13ce608547a5809b62f0
|
||||
|
||||
git submodule update --init
|
||||
make -j$(nproc --ignore=2)
|
||||
make install
|
||||
git describe --all --always --long --dirty > /usr/local/repo-commit-yosys
|
||||
|
||||
# ----------------------------------------------------------------------
|
||||
# nextpnr
|
||||
# ----------------------------------------------------------------------
|
||||
git clone -b nextpnr-0.7 https://github.com/YosysHQ/nextpnr /src/nextpnr
|
||||
cd /src/nextpnr
|
||||
# Make sure the digest is correct and no history has changed
|
||||
git checkout 73b7de74a5769095acb96eb6c6333ffe161452f2
|
||||
|
||||
# Add "Fix handling of RNG seed" #1369
|
||||
git cherry-pick --no-commit 6ca64526bb18ace8690872b09ca1251567c116de
|
||||
|
||||
# Add early exit if place fails on timing
|
||||
sed -i \
|
||||
'345i \ \ \ \ general.add_options()("exit-on-failed-target-frequency",' \
|
||||
common/kernel/command.cc
|
||||
sed -i \
|
||||
'346i \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ "exit if target frequency is not achieved (use together with "' \
|
||||
common/kernel/command.cc
|
||||
sed -i \
|
||||
'347i \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ "--randomize-seed option)");' \
|
||||
common/kernel/command.cc
|
||||
sed -i \
|
||||
'348i \\' \
|
||||
common/kernel/command.cc
|
||||
sed -i \
|
||||
'662s/if (do_route) {/if (do_route \&\& (vm.count("exit-on-failed-target-frequency") ? !had_nonfatal_error : true)) {/' \
|
||||
common/kernel/command.cc
|
||||
sed -i \
|
||||
'244s/bool warn_on_failure = false/bool warn_on_failure = true/' \
|
||||
common/kernel/timing.h
|
||||
|
||||
cmake -DARCH=ice40 .
|
||||
make -j$(nproc --ignore=2)
|
||||
make install
|
||||
git describe --all --always --long --dirty > /usr/local/repo-commit-nextpnr
|
||||
|
||||
# ----------------------------------------------------------------------
|
||||
# icarus verilog
|
||||
# ----------------------------------------------------------------------
|
||||
git clone -b v12_0 --depth=1 https://github.com/steveicarus/iverilog /src/iverilog
|
||||
cd /src/iverilog
|
||||
|
||||
# Make sure the digest is correct and no history has changed
|
||||
git checkout 4fd5291632232fbe1ba49b2c26bb6b2bf1c6c9cf
|
||||
sh autoconf.sh
|
||||
./configure
|
||||
make -j$(nproc --ignore=2)
|
||||
make install
|
||||
git describe --all --always --long --dirty > /usr/local/repo-commit-iverilog
|
||||
|
||||
# ----------------------------------------------------------------------
|
||||
# verilator
|
||||
# ----------------------------------------------------------------------
|
||||
git clone -b v5.028 --depth=1 https://github.com/verilator/verilator /src/verilator
|
||||
cd /src/verilator
|
||||
|
||||
# Make sure the digest is correct and no history has changed
|
||||
git checkout 8ca45df9c75c611989ae5bfc4112a32212c3dacf
|
||||
|
||||
autoconf
|
||||
./configure
|
||||
make -j$(nproc --ignore=2)
|
||||
make test
|
||||
make install
|
||||
git describe --all --always --long --dirty > /usr/local/repo-commit-verilator
|
||||
|
||||
# ----------------------------------------------------------------------
|
||||
# verible
|
||||
# ----------------------------------------------------------------------
|
||||
curl --output /src/verible.tar.gz -L https://github.com/chipsalliance/verible/releases/download/v0.0-3795-gf4d72375/verible-v0.0-3795-gf4d72375-linux-static-x86_64.tar.gz
|
||||
|
||||
# Check against the expected digest
|
||||
sha512sum -c /verible.sha512
|
||||
|
||||
cd /src
|
||||
|
||||
tar xvf verible.tar.gz
|
||||
mv -v verible*/bin/* /usr/local/bin
|
||||
verible-verilog-format --version | head -1 > /usr/local/repo-commit-verible
|
||||
|
||||
# ----------------------------------------------------------------------
|
||||
# cocotb
|
||||
# ----------------------------------------------------------------------
|
||||
git clone -b v1.9.1 https://github.com/cocotb/cocotb.git /src/cocotb
|
||||
cd /src/cocotb
|
||||
pip install . --break-system-packages
|
||||
git describe --all --always --long --dirty > /usr/local/repo-commit-cocotb
|
||||
@ -1 +0,0 @@
|
||||
3e997b8cd494556fa107b96a6daa4e51133208a85b3c0250c0223d7194aedbc98b3f5213fedaee083edd96c317e50057aa9cdc0517197f4638be3834133e2c9f /src/verible.tar.gz
|
||||
@ -2,104 +2,6 @@
|
||||
|
||||
Descriptions of the tagged TKey releases.
|
||||
|
||||
## Upcoming release: Castor
|
||||
|
||||
Overview of changes since TK TK1-24.03 for the Castor milestone so
|
||||
far.
|
||||
|
||||
**Note well**: BREAKING CHANGE! The introduction of the USB Controller
|
||||
Protocol betwen the programs running on the PicoRV32 CPU and the CH552
|
||||
means that device apps that have not been changed to use the protocol
|
||||
will not have any way to communicate with the outside world.
|
||||
|
||||
### General
|
||||
|
||||
- Split repo:
|
||||
|
||||
- tk1, mta1-usb-dev, mta-usb-v1 and mta1-library moves to
|
||||
https://github.com/tillitis/tk1-pcba
|
||||
|
||||
- tp1, mta1-usb-programmer, mta1-library and KiCad-RP Pico moves to
|
||||
https://github.com/tillitis/tp1
|
||||
|
||||
For full change log [see](https://github.com/tillitis/tillitis-key1/compare/TK1-23.03.2...coming-tag)
|
||||
|
||||
### FPGA
|
||||
|
||||
- Security Monitor memory access checks are now more complete.
|
||||
|
||||
- Add SPI main controller mainly to access flash.
|
||||
|
||||
- Add system reset API. Device apps can reset the system and restart
|
||||
the firmware. The FPGA is not reset.
|
||||
|
||||
- Increase clock frequence to 24 MHz.
|
||||
|
||||
- Increase UART baudrate to 500,000.
|
||||
|
||||
- Fix missing clock cycles in timer core.
|
||||
|
||||
- Remove the UART runtime configuration API.
|
||||
|
||||
- Several clean ups and testbench changes.
|
||||
|
||||
- Make Verilator simulation work again.
|
||||
|
||||
- Add hardware clear to send (CTS) signals for communication between
|
||||
UART and CH552.
|
||||
|
||||
### Firmware
|
||||
|
||||
- At startup, fill RAM with random data using the xorwow PRNG, seeded
|
||||
by TRNG.
|
||||
|
||||
- Add support for the new USB Controller Protocol to communicate with
|
||||
different endpoints.
|
||||
|
||||
### CH552
|
||||
|
||||
- Use the new CTS signals for communication over the UART.
|
||||
|
||||
- Add support for two HID endpoints.
|
||||
|
||||
- Add protocol to communicate with the three different endpoints: CDC,
|
||||
HID, debug.
|
||||
|
||||
- Change USB frame sending from a software timer to instead be
|
||||
controlled by the USB Controller Protocol.
|
||||
|
||||
### tkey-builder
|
||||
|
||||
- New versions of:
|
||||
- clang (18.1.3, part of ubuntu 24.04)
|
||||
- icestorm (commit 738af822905fdcf0466e9dd784b9ae4b0b34987f
|
||||
)
|
||||
- yosys (0.45)
|
||||
- nextpnr (0.7) + extra patches for RNG seed handling and early exit
|
||||
- iverilog (v12)
|
||||
- verilator (v5.028)
|
||||
- verible (v0.0-3795)
|
||||
- cocotb (v1.9.1)
|
||||
|
||||
- Remove TKey Programmer (TP) toolchain:
|
||||
|
||||
- gcc-arm-none-eabi: Used for the TKey Programmer firmware, now
|
||||
moved to it's own repo.
|
||||
- libnewlib-arm-none-eabi
|
||||
- libstdc++-arm-none-eabi-newlib
|
||||
- pico-sdk
|
||||
|
||||
TP1 is now in https://github.com/tillitis/tp1
|
||||
|
||||
- Remove Go compiler support.
|
||||
|
||||
### Docs
|
||||
|
||||
- All docs now in READMEs close to the design or code.
|
||||
|
||||
- Protocol docs moved to [the Developer
|
||||
Handbook](https://dev.tillitis.se/)
|
||||
[repo](https://github.com/tillitis/dev-tillitis)
|
||||
|
||||
## TK1-24.03
|
||||
|
||||
|
||||
@ -147,7 +147,6 @@ TESTFW_OBJS = \
|
||||
$(P)/fw/testfw/main.o \
|
||||
$(P)/fw/testfw/start.o \
|
||||
$(P)/fw/tk1/proto.o \
|
||||
$(P)/fw/tk1/assert.o \
|
||||
$(P)/fw/tk1/lib.o \
|
||||
$(P)/fw/tk1/spi.o \
|
||||
$(P)/fw/tk1/flash.o
|
||||
@ -310,8 +309,7 @@ LINT_FLAGS = \
|
||||
-Wno-WIDTHEXPAND \
|
||||
-Wno-UNOPTFLAT \
|
||||
--timescale 1ns/1ns \
|
||||
-DNO_ICE40_DEFAULT_ASSIGNMENTS \
|
||||
-Wno-GENUNNAMED
|
||||
-DNO_ICE40_DEFAULT_ASSIGNMENTS
|
||||
|
||||
lint: $(FPGA_VERILOG_SRCS) \
|
||||
$(SIM_VERILOG_SRCS) \
|
||||
@ -353,8 +351,6 @@ fmt: $(FPGA_VERILOG_SRCS) $(SIM_VERILOG_SRCS) $(VERILATOR_VERILOG_SRCS) $(VERILO
|
||||
# Temporary fix using grep, since the verible with --verify flag only returns
|
||||
# error if the last file is malformatted.
|
||||
checkfmt: $(FPGA_VERILOG_SRCS) $(SIM_VERILOG_SRCS) $(VERILATOR_VERILOG_SRCS) $(VERILOG_SRCS)
|
||||
make -C fw/tk1 checkfmt
|
||||
make -C fw/testfw checkfmt
|
||||
$(FORMAT) $(CHECK_FORMAT_FLAGS) $^ 2>&1 | \
|
||||
grep "Needs formatting" && exit 1 || true
|
||||
.PHONY: checkfmt
|
||||
@ -419,7 +415,6 @@ synth.json: $(FPGA_VERILOG_SRCS) $(VERILOG_SRCS) $(PICORV32_SRCS) bram_fw.hex
|
||||
application_fpga_par.json: synth.json $(P)/data/$(PIN_FILE)
|
||||
$(NEXTPNR_PATH)nextpnr-ice40 \
|
||||
-l application_fpga_par.txt \
|
||||
--seed 4127945014473118301 \
|
||||
--freq $(TARGET_FREQ) \
|
||||
--ignore-loops \
|
||||
--up5k \
|
||||
|
||||
@ -1 +1 @@
|
||||
93e311e4bfa7e2f8c3c89f194b5fbe7b83eff81e6d32fd73c8859d5d76324b48 application_fpga.bin
|
||||
44086edb70377991b57d3f1c231f743fcf0c2c9d2303843ec133f76cc42449a8 application_fpga.bin
|
||||
|
||||
@ -152,9 +152,8 @@ ADDR_CPU_MON_LAST: 0x62
|
||||
Monitors events and state changes in the SoC and handles security
|
||||
violations. Currently checks for:
|
||||
|
||||
1. Trying to access memory that is outside of the defined size of the
|
||||
defined memory areas. *Always enabled*
|
||||
2. Trying to execute instructions in FW\_RAM. *Always enabled.*
|
||||
1. Trying to execute instructions in FW\_RAM. *Always enabled.*
|
||||
2. Trying to access RAM outside of the physical memory. *Always enabled*
|
||||
3. Trying to execute instructions from a memory area in RAM defined by
|
||||
the application.
|
||||
|
||||
|
||||
@ -386,8 +386,7 @@ module tk1 #(
|
||||
// Monitor events and state changes in the SoC, and handle
|
||||
// security violations. We currently check for:
|
||||
//
|
||||
// Any memory access that is outside of the defined size of the
|
||||
// defined memory areas.
|
||||
// Any access to RAM but outside of the size of the physical mem.
|
||||
//
|
||||
// Trying to execute instructions in FW-RAM.
|
||||
//
|
||||
@ -402,77 +401,10 @@ module tk1 #(
|
||||
force_trap_set = 1'h0;
|
||||
|
||||
if (cpu_valid) begin
|
||||
// Outside ROM area
|
||||
if (cpu_addr[31 : 30] == 2'h0 & |cpu_addr[29 : 14]) begin
|
||||
force_trap_set = 1'h1;
|
||||
end
|
||||
|
||||
// Outside RAM area
|
||||
if (cpu_addr[31 : 30] == 2'h1 & |cpu_addr[29 : 17]) begin
|
||||
force_trap_set = 1'h1;
|
||||
end
|
||||
|
||||
// In RESERVED area
|
||||
if (cpu_addr[31 : 30] == 2'h2) begin
|
||||
force_trap_set = 1'h1;
|
||||
end
|
||||
|
||||
// MMIO
|
||||
if (cpu_addr[31 : 30] == 2'h3) begin
|
||||
|
||||
// Outside TRNG
|
||||
if (cpu_addr[29 : 24] == 6'h00 & |cpu_addr[23 : 10]) begin
|
||||
force_trap_set = 1'h1;
|
||||
end
|
||||
|
||||
// Outside TIMER
|
||||
if (cpu_addr[29 : 24] == 6'h01 & |cpu_addr[23 : 10]) begin
|
||||
force_trap_set = 1'h1;
|
||||
end
|
||||
|
||||
// Outside UDS
|
||||
if (cpu_addr[29 : 24] == 6'h02 & |cpu_addr[23 : 5]) begin
|
||||
force_trap_set = 1'h1;
|
||||
end
|
||||
|
||||
// Outside UART
|
||||
if (cpu_addr[29 : 24] == 6'h03 & |cpu_addr[23 : 10]) begin
|
||||
force_trap_set = 1'h1;
|
||||
end
|
||||
|
||||
// Outside TOUCH_SENSE
|
||||
if (cpu_addr[29 : 24] == 6'h04 & |cpu_addr[23 : 10]) begin
|
||||
force_trap_set = 1'h1;
|
||||
end
|
||||
|
||||
// In unused space
|
||||
if ((cpu_addr[29 : 24] > 6'h04) && (cpu_addr[29 : 24] < 6'h10)) begin
|
||||
force_trap_set = 1'h1;
|
||||
end
|
||||
|
||||
// Outside FW_RAM
|
||||
if (cpu_addr[29 : 24] == 6'h10 & |cpu_addr[23 : 11]) begin
|
||||
force_trap_set = 1'h1;
|
||||
end
|
||||
|
||||
// In unused space
|
||||
if ((cpu_addr[29 : 24] > 6'h10) && (cpu_addr[29 : 24] < 6'h21)) begin
|
||||
force_trap_set = 1'h1;
|
||||
end
|
||||
|
||||
// Entire IRQ31 trigger area is accessible
|
||||
|
||||
// In unused space
|
||||
if ((cpu_addr[29 : 24] > 6'h21) && (cpu_addr[29 : 24] < 6'h3f)) begin
|
||||
force_trap_set = 1'h1;
|
||||
end
|
||||
|
||||
// Outside TK1
|
||||
if (cpu_addr[29 : 24] == 6'h3f & |cpu_addr[23 : 10]) begin
|
||||
force_trap_set = 1'h1;
|
||||
end
|
||||
end
|
||||
|
||||
if (cpu_instr) begin
|
||||
if ((cpu_addr >= FW_RAM_FIRST) && (cpu_addr <= FW_RAM_LAST)) begin
|
||||
force_trap_set = 1'h1;
|
||||
|
||||
@ -236,6 +236,7 @@ module tb_tk1 ();
|
||||
//----------------------------------------------------------------
|
||||
task reset_dut;
|
||||
begin
|
||||
$display("--- Toggle reset.");
|
||||
tb_reset_n = 0;
|
||||
#(2 * CLK_PERIOD);
|
||||
tb_reset_n = 1;
|
||||
@ -349,16 +350,12 @@ module tb_tk1 ();
|
||||
reg [31 : 0] read_data;
|
||||
|
||||
tb_address = address;
|
||||
tb_cpu_instr = 1'h0;
|
||||
tb_cpu_valid = 1'h1;
|
||||
tb_we = 1'h0;
|
||||
tb_cs = 1'h1;
|
||||
|
||||
#(CLK_PERIOD);
|
||||
read_data = tb_read_data;
|
||||
|
||||
#(CLK_PERIOD);
|
||||
tb_cpu_valid = 1'h0;
|
||||
tb_cs = 1'h0;
|
||||
end
|
||||
endtask // read_word
|
||||
@ -409,7 +406,7 @@ module tb_tk1 ();
|
||||
task check_equal(input [31 : 0] value, input [31 : 0] expected);
|
||||
begin : check_equal
|
||||
if (value != expected) begin
|
||||
$display("--- Error: Got 0x%08x, expected 0x%08x", value, expected);
|
||||
$display("--- Error: Got 0x%08x, expected 0x%08x", expected, value);
|
||||
error_ctr = error_ctr + 1;
|
||||
end
|
||||
end
|
||||
@ -433,91 +430,6 @@ module tb_tk1 ();
|
||||
end
|
||||
endtask // fetch_instruction
|
||||
|
||||
// cpu_read_word()
|
||||
//
|
||||
// Read a data word from the given CPU address in the DUT.
|
||||
// the word read will be available in the global variable
|
||||
// tb_read_data.
|
||||
//----------------------------------------------------------------
|
||||
task cpu_read_word(input [31 : 0] address);
|
||||
begin : cpu_read_word
|
||||
reg [31 : 0] read_data;
|
||||
|
||||
tb_cpu_addr = address;
|
||||
tb_address = tb_cpu_addr[13:2];
|
||||
tb_cpu_instr = 1'h0;
|
||||
tb_cpu_valid = 1'h1;
|
||||
tb_we = 1'h0;
|
||||
tb_cs = 1'h1;
|
||||
|
||||
#(CLK_PERIOD);
|
||||
read_data = tb_read_data;
|
||||
|
||||
#(CLK_PERIOD);
|
||||
tb_cpu_addr = 32'h0;
|
||||
tb_cpu_valid = 1'h0;
|
||||
tb_address = 12'h0;
|
||||
tb_cs = 1'h0;
|
||||
end
|
||||
endtask // read_word
|
||||
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// cpu_read_check_range_should_trap()
|
||||
//
|
||||
// Read data in a range of CPU addresses (32-bit addresses). Fail
|
||||
// if trap signal is not asserted.
|
||||
// Range is inclusive.
|
||||
//----------------------------------------------------------------
|
||||
task cpu_read_check_range_should_trap(input [31 : 0] start_address, input [31 : 0] end_address);
|
||||
begin : read_check_range_should_not_trap
|
||||
reg [32 : 0] address;
|
||||
reg error_detected;
|
||||
|
||||
address = start_address;
|
||||
error_detected = 0;
|
||||
|
||||
while (!error_detected && (address <= end_address)) begin
|
||||
reset_dut();
|
||||
cpu_read_word(address);
|
||||
if (tb_force_trap == 0) begin
|
||||
$display("--- Error: Expected trap when reading from address 0x%08x", address);
|
||||
error_ctr += 1;
|
||||
error_detected = 1;
|
||||
end
|
||||
address += 1;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// cpu_read_check_range_should_not_trap()
|
||||
//
|
||||
// Read data in a range of CPU addresses (32-bit addresses). Fail
|
||||
// if trap signal is asserted.
|
||||
// Range is inclusive.
|
||||
//----------------------------------------------------------------
|
||||
task cpu_read_check_range_should_not_trap(input [31 : 0] start_address, input [31 : 0] end_address);
|
||||
begin : read_check_should_not_trap
|
||||
reg [31 : 0] address;
|
||||
reg error_detected;
|
||||
|
||||
address = start_address;
|
||||
error_detected = 0;
|
||||
|
||||
while (!error_detected && (address <= end_address)) begin
|
||||
reset_dut();
|
||||
cpu_read_word(address);
|
||||
if (tb_force_trap == 1) begin
|
||||
$display("--- Error: Did not expected trap when reading from address 0x%08x", address);
|
||||
error_ctr += 1;
|
||||
error_detected = 1;
|
||||
end
|
||||
address += 1;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// test1()
|
||||
@ -970,106 +882,6 @@ module tb_tk1 ();
|
||||
end
|
||||
endtask // test10
|
||||
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// test11()
|
||||
// Test security monitor trap ranges.
|
||||
// - Check that reading accessible areas does not trap
|
||||
// - Check that reading the start and end of inaccessible areas
|
||||
// trap
|
||||
//----------------------------------------------------------------
|
||||
task test11;
|
||||
begin
|
||||
tc_ctr = tc_ctr + 1;
|
||||
|
||||
$display("");
|
||||
$display("--- test11: Test trap ranges.");
|
||||
|
||||
// ROM trap range: 0x00004000-0x3fffffff
|
||||
$display("--- test11: ROM");
|
||||
cpu_read_check_range_should_not_trap(32'h0, 32'h3fff);
|
||||
cpu_read_check_range_should_trap(32'h4000, 32'h400f);
|
||||
cpu_read_check_range_should_trap(32'h3ffffff0, 32'h3fffffff);
|
||||
|
||||
// RAM trap range: 0x40020000-0x7fffffff
|
||||
$display("--- test11: RAM");
|
||||
cpu_read_check_range_should_not_trap(32'h40000000, 32'h4000000f);
|
||||
cpu_read_check_range_should_trap(32'h40020000, 32'h4002000f);
|
||||
cpu_read_check_range_should_trap(32'h7ffffff0, 32'h7fffffff);
|
||||
|
||||
// Reserved trap range: 0x80000000-0xbfffffff
|
||||
$display("--- test11: Reserved");
|
||||
cpu_read_check_range_should_trap(32'h80000000, 32'h8000000f);
|
||||
cpu_read_check_range_should_trap(32'hbffffff0, 32'hbfffffff);
|
||||
|
||||
// TRNG trap range: 0xc0000400-0xc0ffffff
|
||||
$display("--- test11: TRNG");
|
||||
cpu_read_check_range_should_not_trap(32'hc0000000, 32'hc00003ff);
|
||||
cpu_read_check_range_should_trap(32'hc0000400, 32'hc000040f);
|
||||
cpu_read_check_range_should_trap(32'hc0fffff0, 32'hc0ffffff);
|
||||
|
||||
// TIMER trap range: 0xc1000400-0xc1ffffff
|
||||
$display("--- test11: TIMER");
|
||||
cpu_read_check_range_should_not_trap(32'hc1000000, 32'hc10003ff);
|
||||
cpu_read_check_range_should_trap(32'hc1000400, 32'hc100040f);
|
||||
cpu_read_check_range_should_trap(32'hc1fffff0, 32'hc1ffffff);
|
||||
|
||||
// UDS trap range: 0xc2000020-0xc2ffffff
|
||||
$display("--- test11: UDS");
|
||||
cpu_read_check_range_should_not_trap(32'hc2000000, 32'hc200001f);
|
||||
cpu_read_check_range_should_trap(32'hc2000020, 32'hc200002f);
|
||||
cpu_read_check_range_should_trap(32'hc2fffff0, 32'hc2ffffff);
|
||||
|
||||
// UART trap range: 0xc3000400-0xc3ffffff
|
||||
$display("--- test11: UART");
|
||||
cpu_read_check_range_should_not_trap(32'hc3000000, 32'hc30003ff);
|
||||
cpu_read_check_range_should_trap(32'hc3000400, 32'hc300040f);
|
||||
cpu_read_check_range_should_trap(32'hc3fffff0, 32'hc3ffffff);
|
||||
|
||||
// TOUCH_SENSE trap range: 0xc4000400-0xc4ffffff
|
||||
$display("--- test11: TOUCH_SENSE");
|
||||
cpu_read_check_range_should_not_trap(32'hc4000000, 32'hc40003ff);
|
||||
cpu_read_check_range_should_trap(32'hc4000400, 32'hc400040f);
|
||||
cpu_read_check_range_should_trap(32'hc4fffff0, 32'hc4ffffff);
|
||||
|
||||
// Unused trap range: 0xc5000000-0xcfffffff
|
||||
$display("--- test11: Unused");
|
||||
cpu_read_check_range_should_trap(32'hc5000000, 32'hc500000f);
|
||||
cpu_read_check_range_should_trap(32'hc5fffff0, 32'hc5ffffff);
|
||||
|
||||
// FW_RAM trap range: 0xd0000800-0xd0ffffff
|
||||
$display("--- test11: FW_RAM");
|
||||
cpu_read_check_range_should_not_trap(32'hd0000000, 32'hd00007ff);
|
||||
cpu_read_check_range_should_trap(32'hd0000800, 32'hd000080f);
|
||||
cpu_read_check_range_should_trap(32'hd0fffff0, 32'hd0ffffff);
|
||||
|
||||
// Unused trap range: 0xd1000000-0xfeffffff
|
||||
$display("--- test11: Unused");
|
||||
cpu_read_check_range_should_trap(32'hd1000000, 32'hd100000f);
|
||||
cpu_read_check_range_should_trap(32'he0fffff0, 32'he0ffffff);
|
||||
|
||||
// IRQ31 No trap range. Entire 0xe1 range is accessible.
|
||||
cpu_read_check_range_should_not_trap(32'he1000000, 32'he100000f);
|
||||
cpu_read_check_range_should_not_trap(32'he1fffff0, 32'he1ffffff);
|
||||
|
||||
// Unused trap range: 0xe2000000-0xfeffffff
|
||||
//
|
||||
$display("--- test11: Unused");
|
||||
cpu_read_check_range_should_trap(32'he2000000, 32'he200000f);
|
||||
cpu_read_check_range_should_trap(32'hfefffff0, 32'hfeffffff);
|
||||
|
||||
// TK1 trap range: 0xff000400-0xffffffff
|
||||
$display("--- test11: TK1");
|
||||
cpu_read_check_range_should_not_trap(32'hff000000, 32'hff0003ff);
|
||||
cpu_read_check_range_should_trap(32'hff000400, 32'hff00040f);
|
||||
cpu_read_check_range_should_trap(32'hfffffff0, 32'hffffffff);
|
||||
|
||||
$display("--- test11: completed.");
|
||||
$display("");
|
||||
end
|
||||
endtask // test11
|
||||
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// exit_with_error_code()
|
||||
//
|
||||
@ -1109,7 +921,6 @@ module tb_tk1 ();
|
||||
test9();
|
||||
test9();
|
||||
test10();
|
||||
test11();
|
||||
|
||||
display_test_result();
|
||||
$display("");
|
||||
|
||||
@ -55,9 +55,6 @@ module uart (
|
||||
input wire rxd,
|
||||
output wire txd,
|
||||
|
||||
input wire ch552_cts,
|
||||
output wire fpga_cts,
|
||||
|
||||
input wire cs,
|
||||
input wire we,
|
||||
input wire [ 7 : 0] address,
|
||||
@ -82,10 +79,10 @@ module uart (
|
||||
// The default bit rate is based on target clock frequency
|
||||
// divided by the bit rate times in order to hit the
|
||||
// center of the bits. I.e.
|
||||
// Clock: 21 MHz, 500 kbps
|
||||
// Divisor = 21E6 / 500E3 = 42
|
||||
// Clock: 21 MHz, 62500 bps
|
||||
// Divisor = 21E6 / 62500 = 336
|
||||
// This also satisfies 1E6 % bps == 0 for the CH552 MCU used for USB-serial
|
||||
localparam DEFAULT_BIT_RATE = 16'd42;
|
||||
localparam DEFAULT_BIT_RATE = 16'd336;
|
||||
localparam DEFAULT_DATA_BITS = 4'h8;
|
||||
localparam DEFAULT_STOP_BITS = 2'h1;
|
||||
|
||||
@ -113,7 +110,6 @@ module uart (
|
||||
reg [31 : 0] tmp_read_data;
|
||||
reg tmp_ready;
|
||||
|
||||
reg [ 1 : 0] ch552_cts_reg;
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// Concurrent connectivity for ports etc.
|
||||
@ -162,24 +158,9 @@ module uart (
|
||||
|
||||
.out_syn (fifo_out_syn),
|
||||
.out_data(fifo_out_data),
|
||||
.out_ack (fifo_out_ack),
|
||||
|
||||
.fpga_cts(fpga_cts)
|
||||
.out_ack (fifo_out_ack)
|
||||
);
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// reg_update
|
||||
//----------------------------------------------------------------
|
||||
always @(posedge clk) begin : reg_update
|
||||
if (!reset_n) begin
|
||||
ch552_cts_reg <= 2'h0;
|
||||
end
|
||||
else begin
|
||||
ch552_cts_reg[0] <= ch552_cts;
|
||||
ch552_cts_reg[1] <= ch552_cts_reg[0];
|
||||
end
|
||||
end // reg_update
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// api
|
||||
//
|
||||
@ -227,7 +208,7 @@ module uart (
|
||||
end
|
||||
|
||||
ADDR_TX_STATUS: begin
|
||||
tmp_read_data = {31'h0, core_txd_ready & ch552_cts_reg[1]};
|
||||
tmp_read_data = {31'h0, core_txd_ready};
|
||||
end
|
||||
|
||||
default: begin
|
||||
|
||||
@ -81,9 +81,10 @@ module uart_core (
|
||||
parameter ERX_SYN = 4;
|
||||
|
||||
parameter ETX_IDLE = 0;
|
||||
parameter ETX_START = 1;
|
||||
parameter ETX_BITS = 2;
|
||||
parameter ETX_STOP = 3;
|
||||
parameter ETX_ACK = 1;
|
||||
parameter ETX_START = 2;
|
||||
parameter ETX_BITS = 3;
|
||||
parameter ETX_STOP = 4;
|
||||
|
||||
|
||||
//----------------------------------------------------------------
|
||||
@ -170,19 +171,19 @@ module uart_core (
|
||||
//----------------------------------------------------------------
|
||||
always @(posedge clk) begin : reg_update
|
||||
if (!reset_n) begin
|
||||
rxd0_reg <= 0;
|
||||
rxd_reg <= 0;
|
||||
rxd0_reg <= 1'b0;
|
||||
rxd_reg <= 1'b0;
|
||||
rxd_byte_reg <= 8'h0;
|
||||
rxd_bit_ctr_reg <= 4'h0;
|
||||
rxd_bitrate_ctr_reg <= 16'h0;
|
||||
rxd_syn_reg <= 0;
|
||||
erx_ctrl_reg <= ERX_IDLE;
|
||||
|
||||
txd_reg <= 1;
|
||||
txd_reg <= 1'b1;
|
||||
txd_byte_reg <= 8'h0;
|
||||
txd_bit_ctr_reg <= 4'h0;
|
||||
txd_bitrate_ctr_reg <= 16'h0;
|
||||
txd_ready_reg <= 1;
|
||||
txd_ready_reg <= 1'b1;
|
||||
etx_ctrl_reg <= ETX_IDLE;
|
||||
end
|
||||
|
||||
@ -245,16 +246,16 @@ module uart_core (
|
||||
//----------------------------------------------------------------
|
||||
always @* begin : rxd_bit_ctr
|
||||
rxd_bit_ctr_new = 4'h0;
|
||||
rxd_bit_ctr_we = 0;
|
||||
rxd_bit_ctr_we = 1'b0;
|
||||
|
||||
if (rxd_bit_ctr_rst) begin
|
||||
rxd_bit_ctr_new = 4'h0;
|
||||
rxd_bit_ctr_we = 1;
|
||||
rxd_bit_ctr_we = 1'b1;
|
||||
end
|
||||
|
||||
else if (rxd_bit_ctr_inc) begin
|
||||
rxd_bit_ctr_new = rxd_bit_ctr_reg + 1'h1;
|
||||
rxd_bit_ctr_we = 1;
|
||||
rxd_bit_ctr_we = 1'b1;
|
||||
end
|
||||
end // rxd_bit_ctr
|
||||
|
||||
@ -266,21 +267,22 @@ module uart_core (
|
||||
// serial interface.
|
||||
//----------------------------------------------------------------
|
||||
always @* begin : rxd_bitrate_ctr
|
||||
rxd_bitrate_ctr_new = 16'h1;
|
||||
rxd_bitrate_ctr_we = 0;
|
||||
rxd_bitrate_ctr_new = 16'h0;
|
||||
rxd_bitrate_ctr_we = 1'h0;
|
||||
|
||||
if (rxd_bitrate_ctr_rst) begin
|
||||
rxd_bitrate_ctr_new = 16'h1;
|
||||
rxd_bitrate_ctr_we = 1;
|
||||
rxd_bitrate_ctr_new = 16'h0;
|
||||
rxd_bitrate_ctr_we = 1'b1;
|
||||
end
|
||||
|
||||
else if (rxd_bitrate_ctr_inc) begin
|
||||
rxd_bitrate_ctr_new = rxd_bitrate_ctr_reg + 1'h1;
|
||||
rxd_bitrate_ctr_we = 1;
|
||||
rxd_bitrate_ctr_we = 1'b1;
|
||||
end
|
||||
end // rxd_bitrate_ctr
|
||||
|
||||
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// txd_bit_ctr
|
||||
//
|
||||
@ -289,16 +291,16 @@ module uart_core (
|
||||
//----------------------------------------------------------------
|
||||
always @* begin : txd_bit_ctr
|
||||
txd_bit_ctr_new = 4'h0;
|
||||
txd_bit_ctr_we = 0;
|
||||
txd_bit_ctr_we = 1'h0;
|
||||
|
||||
if (txd_bit_ctr_rst) begin
|
||||
txd_bit_ctr_new = 4'h0;
|
||||
txd_bit_ctr_we = 1;
|
||||
txd_bit_ctr_we = 1'h1;
|
||||
end
|
||||
|
||||
else if (txd_bit_ctr_inc) begin
|
||||
txd_bit_ctr_new = txd_bit_ctr_reg + 1'h1;
|
||||
txd_bit_ctr_we = 1;
|
||||
txd_bit_ctr_we = 1'b1;
|
||||
end
|
||||
end // txd_bit_ctr
|
||||
|
||||
@ -310,11 +312,11 @@ module uart_core (
|
||||
// serial interface.
|
||||
//----------------------------------------------------------------
|
||||
always @* begin : txd_bitrate_ctr
|
||||
txd_bitrate_ctr_new = 16'h1;
|
||||
txd_bitrate_ctr_new = 16'h0;
|
||||
txd_bitrate_ctr_we = 0;
|
||||
|
||||
if (txd_bitrate_ctr_rst) begin
|
||||
txd_bitrate_ctr_new = 16'h1;
|
||||
txd_bitrate_ctr_new = 16'h0;
|
||||
txd_bitrate_ctr_we = 1;
|
||||
end
|
||||
|
||||
@ -348,32 +350,25 @@ module uart_core (
|
||||
ERX_IDLE: begin
|
||||
if (!rxd_reg) begin
|
||||
// Possible start bit detected.
|
||||
rxd_bitrate_ctr_inc = 1;
|
||||
rxd_bitrate_ctr_rst = 1;
|
||||
erx_ctrl_new = ERX_START;
|
||||
erx_ctrl_we = 1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
ERX_START: begin
|
||||
rxd_bitrate_ctr_inc = 1;
|
||||
if (rxd_reg) begin
|
||||
// Just a glitch.
|
||||
rxd_bitrate_ctr_rst = 1;
|
||||
erx_ctrl_new = ERX_IDLE;
|
||||
erx_ctrl_we = 1;
|
||||
end
|
||||
|
||||
else begin
|
||||
if (rxd_bitrate_ctr_reg < half_bit_rate) begin
|
||||
rxd_bitrate_ctr_inc = 1;
|
||||
end
|
||||
|
||||
else begin
|
||||
// Start bit assumed.
|
||||
// We are in the middle of the start bit.
|
||||
// Start sampling data.
|
||||
rxd_bitrate_ctr_rst = 1;
|
||||
if (rxd_bitrate_ctr_reg == half_bit_rate) begin
|
||||
// start bit assumed. We start sampling data.
|
||||
rxd_bit_ctr_rst = 1;
|
||||
rxd_bitrate_ctr_rst = 1;
|
||||
erx_ctrl_new = ERX_BITS;
|
||||
erx_ctrl_we = 1;
|
||||
end
|
||||
@ -387,14 +382,11 @@ module uart_core (
|
||||
end
|
||||
|
||||
else begin
|
||||
if (rxd_bit_ctr_reg < data_bits) begin
|
||||
rxd_bitrate_ctr_rst = 1;
|
||||
rxd_byte_we = 1;
|
||||
rxd_bit_ctr_inc = 1;
|
||||
rxd_byte_we = 1; // We are in the middle of a data bit, make a sample
|
||||
end
|
||||
|
||||
else begin
|
||||
erx_ctrl_new = ERX_STOP; // We are now in the middle of the stop bit
|
||||
rxd_bitrate_ctr_rst = 1;
|
||||
if (rxd_bit_ctr_reg == (data_bits - 1)) begin
|
||||
erx_ctrl_new = ERX_STOP;
|
||||
erx_ctrl_we = 1;
|
||||
end
|
||||
end
|
||||
@ -402,13 +394,8 @@ module uart_core (
|
||||
|
||||
|
||||
ERX_STOP: begin
|
||||
// stop_bits can be removed from line below if we are only using one stop bit
|
||||
if (rxd_bitrate_ctr_reg < (bit_rate * stop_bits)) begin
|
||||
rxd_bitrate_ctr_inc = 1;
|
||||
end
|
||||
|
||||
else begin
|
||||
rxd_bitrate_ctr_rst = 1;
|
||||
if (rxd_bitrate_ctr_reg == bit_rate * stop_bits) begin
|
||||
rxd_syn_new = 1;
|
||||
rxd_syn_we = 1;
|
||||
erx_ctrl_new = ERX_SYN;
|
||||
@ -457,15 +444,22 @@ module uart_core (
|
||||
ETX_IDLE: begin
|
||||
txd_new = 1;
|
||||
txd_we = 1;
|
||||
txd_bit_ctr_rst = 1;
|
||||
if (txd_syn) begin
|
||||
txd_new = 0;
|
||||
txd_we = 1;
|
||||
txd_byte_new = txd_data;
|
||||
txd_byte_we = 1;
|
||||
txd_ready_new = 0;
|
||||
txd_ready_we = 1;
|
||||
txd_bitrate_ctr_rst = 1;
|
||||
etx_ctrl_new = ETX_ACK;
|
||||
etx_ctrl_we = 1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
ETX_ACK: begin
|
||||
if (!txd_syn) begin
|
||||
txd_new = 0;
|
||||
txd_we = 1;
|
||||
etx_ctrl_new = ETX_START;
|
||||
etx_ctrl_we = 1;
|
||||
end
|
||||
@ -473,17 +467,14 @@ module uart_core (
|
||||
|
||||
|
||||
ETX_START: begin
|
||||
if (txd_bitrate_ctr_reg < bit_rate) begin
|
||||
txd_bitrate_ctr_inc = 1;
|
||||
if (txd_bitrate_ctr_reg == bit_rate) begin
|
||||
txd_bit_ctr_rst = 1;
|
||||
etx_ctrl_new = ETX_BITS;
|
||||
etx_ctrl_we = 1;
|
||||
end
|
||||
|
||||
else begin
|
||||
txd_bitrate_ctr_rst = 1;
|
||||
txd_bit_ctr_inc = 1;
|
||||
txd_new = txd_byte_reg[txd_bit_ctr_reg[2 : 0]];
|
||||
txd_we = 1;
|
||||
etx_ctrl_new = ETX_BITS;
|
||||
etx_ctrl_we = 1;
|
||||
txd_bitrate_ctr_inc = 1;
|
||||
end
|
||||
end
|
||||
|
||||
@ -495,32 +486,25 @@ module uart_core (
|
||||
|
||||
else begin
|
||||
txd_bitrate_ctr_rst = 1;
|
||||
|
||||
if (txd_bit_ctr_reg < data_bits) begin
|
||||
txd_bit_ctr_inc = 1;
|
||||
txd_new = txd_byte_reg[txd_bit_ctr_reg[2 : 0]];
|
||||
txd_we = 1;
|
||||
end
|
||||
|
||||
else begin
|
||||
if (txd_bit_ctr_reg == data_bits) begin
|
||||
txd_new = 1;
|
||||
txd_we = 1;
|
||||
etx_ctrl_new = ETX_STOP;
|
||||
etx_ctrl_we = 1;
|
||||
end
|
||||
|
||||
else begin
|
||||
txd_new = txd_byte_reg[txd_bit_ctr_reg[2 : 0]];
|
||||
txd_we = 1;
|
||||
txd_bit_ctr_inc = 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
ETX_STOP: begin
|
||||
// stop_bits can be removed from line below if we are only using one stop bit
|
||||
if (txd_bitrate_ctr_reg < (bit_rate * stop_bits)) begin
|
||||
txd_bitrate_ctr_inc = 1;
|
||||
end
|
||||
|
||||
else begin
|
||||
txd_bitrate_ctr_rst = 1;
|
||||
txd_bit_ctr_rst = 1;
|
||||
if (txd_bitrate_ctr_reg == bit_rate * stop_bits) begin
|
||||
txd_ready_new = 1;
|
||||
txd_ready_we = 1;
|
||||
etx_ctrl_new = ETX_IDLE;
|
||||
|
||||
@ -48,9 +48,7 @@ module uart_fifo (
|
||||
|
||||
output wire out_syn,
|
||||
output wire [7 : 0] out_data,
|
||||
input wire out_ack,
|
||||
|
||||
output wire fpga_cts
|
||||
input wire out_ack
|
||||
);
|
||||
|
||||
|
||||
@ -77,7 +75,6 @@ module uart_fifo (
|
||||
reg in_ack_reg;
|
||||
reg in_ack_new;
|
||||
|
||||
reg fpga_cts_reg;
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// Wires
|
||||
@ -93,7 +90,6 @@ module uart_fifo (
|
||||
assign out_syn = ~fifo_empty;
|
||||
assign out_data = fifo_mem[out_ptr_reg];
|
||||
assign fifo_bytes = byte_ctr_reg;
|
||||
assign fpga_cts = fpga_cts_reg;
|
||||
|
||||
|
||||
//----------------------------------------------------------------
|
||||
@ -105,7 +101,6 @@ module uart_fifo (
|
||||
out_ptr_reg <= 9'h0;
|
||||
byte_ctr_reg <= 9'h0;
|
||||
in_ack_reg <= 1'h0;
|
||||
fpga_cts_reg <= 1'h1;
|
||||
end
|
||||
else begin
|
||||
in_ack_reg <= in_ack_new;
|
||||
@ -125,14 +120,6 @@ module uart_fifo (
|
||||
if (byte_ctr_we) begin
|
||||
byte_ctr_reg <= byte_ctr_new;
|
||||
end
|
||||
|
||||
if (byte_ctr_reg >= 9'd486) begin // FIFO is filled to ~95% or more
|
||||
fpga_cts_reg <= 0; // Signal to not send more data
|
||||
end
|
||||
else begin
|
||||
fpga_cts_reg <= 1; // Signal to send more data
|
||||
end
|
||||
|
||||
end
|
||||
end // reg_update
|
||||
|
||||
|
||||
@ -14,8 +14,8 @@
|
||||
# UART.
|
||||
set_io interface_rx 26
|
||||
set_io interface_tx 25
|
||||
set_io interface_ch552_cts 27
|
||||
set_io interface_fpga_cts 28
|
||||
# set_io interface_cts 27
|
||||
# set_io interface_rts 28
|
||||
|
||||
|
||||
# SPI master to flash memory.
|
||||
|
||||
@ -1 +1 @@
|
||||
5e655ba4f25e7f5bc033ce0d9707c9a0b8990258c4b87470c2bcef90d50df79813705c1ef9d22c8670a37aff68f0e5146e5d0c21406916aabf7704579eb7f15c firmware.bin
|
||||
edb39fca7dafb8ea0b89fdeecd960d7656e14ce461e49af97160a8bd6e67d9987e816adad37ba0fcfa63d107c3160988e4c3423ce4a71c39544bc0045888fec1 firmware.bin
|
||||
|
||||
@ -37,38 +37,15 @@ memory access control.
|
||||
|
||||
## Communication
|
||||
|
||||
The firmware communicates with the client using the
|
||||
`UART_{RX,TX}_{STATUS,DATA}` registers. On top of that is uses three
|
||||
protocols: The USB Mode protocol, the TKey framing protocol, and the
|
||||
firmware's own protocol.
|
||||
|
||||
To communicate between the CPU and the CH552 USB controller it uses an
|
||||
internal protocol, used only within the TKey, which we call the USB
|
||||
Mode Protocol. It is used in both directions.
|
||||
|
||||
| *Name* | *Size* | *Comment* |
|
||||
|----------|-----------|------------------------------------|
|
||||
| Endpoint | 1B | Origin or destination USB endpoint |
|
||||
| Length | 1B | Number of bytes following |
|
||||
| Payload | See above | Actual data from or to firmware |
|
||||
|
||||
The different endpoints:
|
||||
|
||||
| *Name* | *Value* | *Comment* |
|
||||
|--------|---------|---------------------------------------------------------------------|
|
||||
| CTRL | 0x20 | A USB HID special debug pipe. Useful for debug prints. |
|
||||
| CDC | 0x40 | USB CDC-ACM, a serial port on the client. |
|
||||
| HID | 0x80 | A USB HID security token device, useful for FIDO-type applications. |
|
||||
|
||||
On top of the USB Mode Protocol is [the TKey Framing
|
||||
Protocol](https://dev.tillitis.se/protocol/) which is described in the
|
||||
Developer Handbook.
|
||||
The firmware communicates to the host via the
|
||||
`UART_{RX,TX}_{STATUS,DATA}` registers, using the framing protocol
|
||||
described in the [Framing
|
||||
Protocol](https://dev.tillitis.se/protocol/).
|
||||
|
||||
The firmware uses a protocol on top of this framing layer which is
|
||||
used to bootstrap an application. All commands are initiated by the
|
||||
used to bootstrap the application. All commands are initiated by the
|
||||
client. All commands receive a reply. See [Firmware
|
||||
protocol](http://dev.tillitis.se/protocol/#firmware-protocol) in the
|
||||
Dev Handbook for specific details.
|
||||
protocol](#firmware-protocol) for specific details.
|
||||
|
||||
## Memory constraints
|
||||
|
||||
@ -160,9 +137,12 @@ application mode, but with no privileged access.
|
||||
Firmware loads the application at the start of RAM (`0x4000_0000`). It
|
||||
uses the special FW\_RAM for its own stack.
|
||||
|
||||
When the firmware starts it clears all FW\_RAM, then sets up a stack
|
||||
there before jumping to `main()`.
|
||||
|
||||
When reset is released, the CPU starts executing the firmware. It
|
||||
begins by clearing all CPU registers, clears all FW\_RAM, sets up a
|
||||
stack for itself there, and then jumps to `main()`.
|
||||
begins by clearing all CPU registers, and then sets up a stack for
|
||||
itself and then jumps to main().
|
||||
|
||||
Beginning at `main()` it sets up the "system calls", then fills the
|
||||
entire RAM with pseudo random data and setting up the RAM address and
|
||||
@ -207,8 +187,8 @@ Typical expected use scenario:
|
||||
stack. After this it performs no more function calls and uses no
|
||||
more automatic variables.
|
||||
|
||||
8. Firmware starts the application by first switching from firmware
|
||||
mode to application mode by writing to the `SYSTEM_MODE_CTRL`
|
||||
8. Firmware starts the application by first switching to from
|
||||
firmware mode to application mode by writing to the `SYSTEM_MODE_CTRL`
|
||||
register. In this mode the MMIO region is restricted, e.g. some
|
||||
registers are removed (`UDS`), and some are switched from
|
||||
read/write to read-only (see [the memory
|
||||
|
||||
@ -49,7 +49,6 @@ TESTAPP_OBJS = \
|
||||
$(P)/main.o \
|
||||
$(P)/crt0.o \
|
||||
$(P)/syscall.o \
|
||||
$(P)/../tk1/assert.o \
|
||||
$(P)/../tk1/led.o \
|
||||
$(P)/../tk1/lib.o \
|
||||
$(P)/../tk1/proto.o
|
||||
|
||||
@ -11,8 +11,6 @@
|
||||
#include "../tk1_mem.h"
|
||||
#include "syscall.h"
|
||||
|
||||
#define USBMODE_PACKET_SIZE 64
|
||||
|
||||
// clang-format off
|
||||
volatile uint32_t *tk1name0 = (volatile uint32_t *)TK1_MMIO_TK1_NAME0;
|
||||
volatile uint32_t *tk1name1 = (volatile uint32_t *)TK1_MMIO_TK1_NAME1;
|
||||
@ -33,68 +31,38 @@ volatile uint32_t *trng_entropy = (volatile uint32_t *)TK1_MMIO_TRNG_ENTROPY
|
||||
#define UDI_WORDS 2
|
||||
#define CDI_WORDS 8
|
||||
|
||||
static void write_with_header(const uint8_t *buf, size_t nbytes, enum mode mode)
|
||||
void *memcpy(void *dest, const void *src, size_t n)
|
||||
{
|
||||
// Append USB Mode Protocol header:
|
||||
// 1 byte mode
|
||||
// 1 byte length
|
||||
writebyte(mode);
|
||||
writebyte(nbytes);
|
||||
uint8_t *src_byte = (uint8_t *)src;
|
||||
uint8_t *dest_byte = (uint8_t *)dest;
|
||||
|
||||
for (int i = 0; i < nbytes; i++) {
|
||||
writebyte(buf[i]);
|
||||
}
|
||||
for (int i = 0; i < n; i++) {
|
||||
dest_byte[i] = src_byte[i];
|
||||
}
|
||||
|
||||
static void write(const uint8_t *buf, size_t nbytes)
|
||||
return dest;
|
||||
}
|
||||
|
||||
void puts(char *reason)
|
||||
{
|
||||
uint8_t len;
|
||||
|
||||
while (nbytes > 0) {
|
||||
// We split the data into chunks that will fit in the
|
||||
// USB Mode Protocol with some spare change.
|
||||
len =
|
||||
nbytes < USBMODE_PACKET_SIZE ? nbytes : USBMODE_PACKET_SIZE;
|
||||
|
||||
write_with_header((const uint8_t *)buf, len, MODE_CDC);
|
||||
|
||||
buf += len;
|
||||
nbytes -= len;
|
||||
for (char *c = reason; *c != '\0'; c++) {
|
||||
writebyte(*c);
|
||||
}
|
||||
}
|
||||
|
||||
unsigned strlen(const char *str)
|
||||
void putsn(char *p, int n)
|
||||
{
|
||||
const char *s;
|
||||
|
||||
for (s = str; *s; ++s)
|
||||
;
|
||||
|
||||
return (s - str);
|
||||
for (int i = 0; i < n; i++) {
|
||||
writebyte(p[i]);
|
||||
}
|
||||
|
||||
void puts(char *buf)
|
||||
{
|
||||
size_t nbytes = strlen(buf);
|
||||
|
||||
write((const uint8_t *)buf, nbytes);
|
||||
}
|
||||
|
||||
void hex(uint8_t buf[2], const uint8_t c)
|
||||
{
|
||||
unsigned int upper = (c >> 4) & 0xf;
|
||||
unsigned int lower = c & 0xf;
|
||||
|
||||
buf[0] = upper < 10 ? '0' + upper : 'a' - 10 + upper;
|
||||
buf[1] = lower < 10 ? '0' + lower : 'a' - 10 + lower;
|
||||
}
|
||||
|
||||
void puthex(uint8_t c)
|
||||
{
|
||||
uint8_t buf[2];
|
||||
|
||||
hex(buf, c);
|
||||
write(buf, 2);
|
||||
unsigned int upper = (c >> 4) & 0xf;
|
||||
unsigned int lower = c & 0xf;
|
||||
writebyte(upper < 10 ? '0' + upper : 'a' - 10 + upper);
|
||||
writebyte(lower < 10 ? '0' + lower : 'a' - 10 + lower);
|
||||
}
|
||||
|
||||
void puthexn(uint8_t *p, int n)
|
||||
@ -104,6 +72,24 @@ void puthexn(uint8_t *p, int n)
|
||||
}
|
||||
}
|
||||
|
||||
void hexdump(void *buf, int len)
|
||||
{
|
||||
uint8_t *byte_buf = (uint8_t *)buf;
|
||||
|
||||
for (int i = 0; i < len; i++) {
|
||||
puthex(byte_buf[i]);
|
||||
if (i % 2 == 1) {
|
||||
writebyte(' ');
|
||||
}
|
||||
|
||||
if (i != 1 && i % 16 == 1) {
|
||||
puts("\r\n");
|
||||
}
|
||||
}
|
||||
|
||||
puts("\r\n");
|
||||
}
|
||||
|
||||
void reverseword(uint32_t *wordp)
|
||||
{
|
||||
*wordp = ((*wordp & 0xff000000) >> 24) | ((*wordp & 0x00ff0000) >> 8) |
|
||||
@ -121,6 +107,42 @@ uint32_t wait_timer_tick(uint32_t last_timer)
|
||||
}
|
||||
}
|
||||
|
||||
void zero_fwram(void)
|
||||
{
|
||||
for (int i = 0; i < TK1_MMIO_FW_RAM_SIZE; i++) {
|
||||
fw_ram[i] = 0x00;
|
||||
}
|
||||
}
|
||||
|
||||
int check_fwram_zero_except(unsigned int offset, uint8_t expected_val)
|
||||
{
|
||||
int failed = 0;
|
||||
for (unsigned int i = 0; i < TK1_MMIO_FW_RAM_SIZE; i++) {
|
||||
uint32_t addr = TK1_MMIO_FW_RAM_BASE + i;
|
||||
uint8_t *p = (uint8_t *)addr;
|
||||
uint8_t val = *(volatile uint8_t *)p;
|
||||
int failed_now = 0;
|
||||
if (i == offset) {
|
||||
if (val != expected_val) {
|
||||
failed_now = 1;
|
||||
puts(" wrong value at: ");
|
||||
}
|
||||
} else {
|
||||
if (val != 0) {
|
||||
failed_now = 1;
|
||||
puts(" not zero at: ");
|
||||
}
|
||||
}
|
||||
if (failed_now) {
|
||||
failed = 1;
|
||||
reverseword(&addr);
|
||||
puthexn((uint8_t *)&addr, 4);
|
||||
puts("\r\n");
|
||||
}
|
||||
}
|
||||
return failed;
|
||||
}
|
||||
|
||||
void failmsg(char *s)
|
||||
{
|
||||
puts("FAIL: ");
|
||||
@ -130,25 +152,23 @@ void failmsg(char *s)
|
||||
|
||||
int main(void)
|
||||
{
|
||||
uint8_t in = 0;
|
||||
uint8_t mode = 0;
|
||||
uint8_t mode_bytes_left = 0;
|
||||
uint8_t in;
|
||||
|
||||
set_led(LED_BLUE);
|
||||
|
||||
// Wait for terminal program and a character to be typed
|
||||
in = readbyte(&mode, &mode_bytes_left);
|
||||
in = readbyte();
|
||||
|
||||
puts("\r\nI'm testapp on:");
|
||||
// Output the TK1 core's NAME0 and NAME1
|
||||
uint32_t name;
|
||||
wordcpy_s(&name, 1, (void *)tk1name0, 1);
|
||||
reverseword(&name);
|
||||
write((const uint8_t *)&name, 4);
|
||||
putsn((char *)&name, 4);
|
||||
puts(" ");
|
||||
wordcpy_s(&name, 1, (void *)tk1name1, 1);
|
||||
reverseword(&name);
|
||||
write((const uint8_t *)&name, 4);
|
||||
putsn((char *)&name, 4);
|
||||
puts("\r\n");
|
||||
|
||||
uint32_t zeros[8];
|
||||
@ -268,13 +288,10 @@ int main(void)
|
||||
|
||||
puts("Now echoing what you type...Type + to reset device\r\n");
|
||||
for (;;) {
|
||||
in = readbyte(&mode, &mode_bytes_left);
|
||||
in = readbyte(); // blocks
|
||||
if (in == '+') {
|
||||
syscall(TK1_SYSCALL_RESET, 0);
|
||||
}
|
||||
|
||||
writebyte(MODE_CDC);
|
||||
writebyte(1);
|
||||
writebyte(in);
|
||||
}
|
||||
}
|
||||
|
||||
@ -9,8 +9,6 @@
|
||||
#include "../tk1/types.h"
|
||||
#include "../tk1_mem.h"
|
||||
|
||||
#define USBMODE_PACKET_SIZE 64
|
||||
|
||||
// clang-format off
|
||||
volatile uint32_t *tk1name0 = (volatile uint32_t *)TK1_MMIO_TK1_NAME0;
|
||||
volatile uint32_t *tk1name1 = (volatile uint32_t *)TK1_MMIO_TK1_NAME1;
|
||||
@ -43,68 +41,26 @@ void *memcpy(void *dest, const void *src, size_t n)
|
||||
return dest;
|
||||
}
|
||||
|
||||
static void write_with_header(const uint8_t *buf, size_t nbytes, enum mode mode)
|
||||
void puts(char *reason)
|
||||
{
|
||||
// Append USB Mode Protocol header:
|
||||
// 1 byte mode
|
||||
// 1 byte length
|
||||
writebyte(mode);
|
||||
writebyte(nbytes);
|
||||
|
||||
for (int i = 0; i < nbytes; i++) {
|
||||
writebyte(buf[i]);
|
||||
for (char *c = reason; *c != '\0'; c++) {
|
||||
writebyte(*c);
|
||||
}
|
||||
}
|
||||
|
||||
static void write(const uint8_t *buf, size_t nbytes)
|
||||
void putsn(char *p, int n)
|
||||
{
|
||||
uint8_t len;
|
||||
|
||||
while (nbytes > 0) {
|
||||
// We split the data into chunks that will fit in the
|
||||
// USB Mode Protocol with some spare change.
|
||||
len =
|
||||
nbytes < USBMODE_PACKET_SIZE ? nbytes : USBMODE_PACKET_SIZE;
|
||||
|
||||
write_with_header((const uint8_t *)buf, len, MODE_CDC);
|
||||
|
||||
buf += len;
|
||||
nbytes -= len;
|
||||
for (int i = 0; i < n; i++) {
|
||||
writebyte(p[i]);
|
||||
}
|
||||
}
|
||||
|
||||
unsigned strlen(const char *str)
|
||||
{
|
||||
const char *s;
|
||||
|
||||
for (s = str; *s; ++s)
|
||||
;
|
||||
|
||||
return (s - str);
|
||||
}
|
||||
|
||||
void puts(char *buf)
|
||||
{
|
||||
size_t nbytes = strlen(buf);
|
||||
|
||||
write((const uint8_t *)buf, nbytes);
|
||||
}
|
||||
|
||||
void hex(uint8_t buf[2], const uint8_t c)
|
||||
{
|
||||
unsigned int upper = (c >> 4) & 0xf;
|
||||
unsigned int lower = c & 0xf;
|
||||
|
||||
buf[0] = upper < 10 ? '0' + upper : 'a' - 10 + upper;
|
||||
buf[1] = lower < 10 ? '0' + lower : 'a' - 10 + lower;
|
||||
}
|
||||
|
||||
void puthex(uint8_t c)
|
||||
{
|
||||
uint8_t buf[2];
|
||||
|
||||
hex(buf, c);
|
||||
write(buf, 2);
|
||||
unsigned int upper = (c >> 4) & 0xf;
|
||||
unsigned int lower = c & 0xf;
|
||||
writebyte(upper < 10 ? '0' + upper : 'a' - 10 + upper);
|
||||
writebyte(lower < 10 ? '0' + lower : 'a' - 10 + lower);
|
||||
}
|
||||
|
||||
void puthexn(uint8_t *p, int n)
|
||||
@ -121,7 +77,7 @@ void hexdump(void *buf, int len)
|
||||
for (int i = 0; i < len; i++) {
|
||||
puthex(byte_buf[i]);
|
||||
if (i % 2 == 1) {
|
||||
puts(" ");
|
||||
writebyte(' ');
|
||||
}
|
||||
|
||||
if (i != 1 && i % 16 == 1) {
|
||||
@ -194,10 +150,7 @@ void failmsg(char *s)
|
||||
|
||||
int main(void)
|
||||
{
|
||||
uint8_t in = 0;
|
||||
uint8_t mode = 0;
|
||||
uint8_t mode_bytes_left = 0;
|
||||
|
||||
uint8_t in;
|
||||
// Hard coded test UDS in ../../data/uds.hex
|
||||
// clang-format off
|
||||
uint32_t uds_test[8] = {
|
||||
@ -213,18 +166,18 @@ int main(void)
|
||||
// clang-format on
|
||||
|
||||
// Wait for terminal program and a character to be typed
|
||||
in = readbyte(&mode, &mode_bytes_left);
|
||||
in = readbyte();
|
||||
|
||||
puts("\r\nI'm testfw on:");
|
||||
// Output the TK1 core's NAME0 and NAME1
|
||||
uint32_t name;
|
||||
wordcpy_s(&name, 1, (void *)tk1name0, 1);
|
||||
reverseword(&name);
|
||||
write((const uint8_t *)&name, 4);
|
||||
putsn((char *)&name, 4);
|
||||
puts(" ");
|
||||
wordcpy_s(&name, 1, (void *)tk1name1, 1);
|
||||
reverseword(&name);
|
||||
write((const uint8_t *)&name, 4);
|
||||
putsn((char *)&name, 4);
|
||||
puts("\r\n");
|
||||
|
||||
uint32_t zeros[8];
|
||||
@ -315,8 +268,8 @@ int main(void)
|
||||
}
|
||||
|
||||
puts("\r\nTesting timer... 3");
|
||||
// Matching clock at 21 MHz, giving us timer in seconds
|
||||
*timer_prescaler = 21 * 1000000;
|
||||
// Matching clock at 18 MHz, giving us timer in seconds
|
||||
*timer_prescaler = 18 * 1000000;
|
||||
|
||||
// Test timer expiration after 1s
|
||||
*timer = 1;
|
||||
@ -359,7 +312,6 @@ int main(void)
|
||||
}
|
||||
|
||||
puts("\r\nHere are 256 bytes from the TRNG:\r\n");
|
||||
|
||||
for (int j = 0; j < 8; j++) {
|
||||
for (int i = 0; i < 8; i++) {
|
||||
while ((*trng_status &
|
||||
@ -375,10 +327,7 @@ int main(void)
|
||||
|
||||
puts("Now echoing what you type...\r\n");
|
||||
for (;;) {
|
||||
in = readbyte(&mode, &mode_bytes_left);
|
||||
|
||||
writebyte(MODE_CDC);
|
||||
writebyte(1);
|
||||
in = readbyte(); // blocks
|
||||
writebyte(in);
|
||||
}
|
||||
}
|
||||
|
||||
@ -420,9 +420,6 @@ int main(void)
|
||||
/*@+mustfreeonly@*/
|
||||
ctx.use_uss = FALSE;
|
||||
|
||||
uint8_t mode = 0;
|
||||
uint8_t mode_bytes_left = 0;
|
||||
|
||||
scramble_ram();
|
||||
|
||||
#if defined(SIMULATION)
|
||||
@ -432,8 +429,7 @@ int main(void)
|
||||
for (;;) {
|
||||
switch (state) {
|
||||
case FW_STATE_INITIAL:
|
||||
if (readcommand(&hdr, cmd, state, &mode,
|
||||
&mode_bytes_left) == -1) {
|
||||
if (readcommand(&hdr, cmd, state) == -1) {
|
||||
state = FW_STATE_FAIL;
|
||||
break;
|
||||
}
|
||||
@ -442,8 +438,7 @@ int main(void)
|
||||
break;
|
||||
|
||||
case FW_STATE_LOADING:
|
||||
if (readcommand(&hdr, cmd, state, &mode,
|
||||
&mode_bytes_left) == -1) {
|
||||
if (readcommand(&hdr, cmd, state) == -1) {
|
||||
state = FW_STATE_FAIL;
|
||||
break;
|
||||
}
|
||||
|
||||
@ -22,8 +22,7 @@ static uint8_t genhdr(uint8_t id, uint8_t endpoint, uint8_t status,
|
||||
enum cmdlen len);
|
||||
static int parseframe(uint8_t b, struct frame_header *hdr);
|
||||
static void write(uint8_t *buf, size_t nbytes);
|
||||
static int read(uint8_t *buf, size_t bufsize, size_t nbytes, uint8_t *mode,
|
||||
uint8_t *mode_bytes_left);
|
||||
static int read(uint8_t *buf, size_t bufsize, size_t nbytes);
|
||||
static size_t bytelen(enum cmdlen cmdlen);
|
||||
|
||||
static uint8_t genhdr(uint8_t id, uint8_t endpoint, uint8_t status,
|
||||
@ -32,13 +31,12 @@ static uint8_t genhdr(uint8_t id, uint8_t endpoint, uint8_t status,
|
||||
return (id << 5) | (endpoint << 3) | (status << 2) | len;
|
||||
}
|
||||
|
||||
int readcommand(struct frame_header *hdr, uint8_t *cmd, int state,
|
||||
uint8_t *mode, uint8_t *mode_bytes_left)
|
||||
int readcommand(struct frame_header *hdr, uint8_t *cmd, int state)
|
||||
{
|
||||
uint8_t in = 0;
|
||||
|
||||
set_led((state == FW_STATE_LOADING) ? LED_BLACK : LED_WHITE);
|
||||
in = readbyte(mode, mode_bytes_left);
|
||||
in = readbyte();
|
||||
|
||||
if (parseframe(in, hdr) == -1) {
|
||||
htif_puts("Couldn't parse header\n");
|
||||
@ -47,7 +45,7 @@ int readcommand(struct frame_header *hdr, uint8_t *cmd, int state,
|
||||
|
||||
(void)memset(cmd, 0, CMDLEN_MAXBYTES);
|
||||
// Now we know the size of the cmd frame, read it all
|
||||
if (read(cmd, CMDLEN_MAXBYTES, hdr->len, mode, mode_bytes_left) != 0) {
|
||||
if (read(cmd, CMDLEN_MAXBYTES, hdr->len) != 0) {
|
||||
htif_puts("read: buffer overrun\n");
|
||||
return -1;
|
||||
}
|
||||
@ -117,10 +115,6 @@ void fwreply(struct frame_header hdr, enum fwcmd rspcode, uint8_t *buf)
|
||||
|
||||
nbytes = bytelen(len);
|
||||
|
||||
// Mode Protocol Header
|
||||
writebyte(MODE_CDC);
|
||||
writebyte(2);
|
||||
|
||||
// Frame Protocol Header
|
||||
writebyte(genhdr(hdr.id, hdr.endpoint, 0x0, len));
|
||||
|
||||
@ -128,19 +122,7 @@ void fwreply(struct frame_header hdr, enum fwcmd rspcode, uint8_t *buf)
|
||||
writebyte(rspcode);
|
||||
nbytes--;
|
||||
|
||||
while (nbytes > 0) {
|
||||
// Limit transfers to 64 bytes (2 byte header + 62 byte data) to
|
||||
// fit in a single USB frame.
|
||||
size_t tx_count = nbytes > 62 ? 62 : nbytes;
|
||||
// Mode Protocol Header
|
||||
writebyte(MODE_CDC);
|
||||
writebyte(tx_count & 0xff);
|
||||
|
||||
// Data
|
||||
write(buf, tx_count);
|
||||
nbytes -= tx_count;
|
||||
buf += tx_count;
|
||||
}
|
||||
write(buf, nbytes);
|
||||
}
|
||||
|
||||
void writebyte(uint8_t b)
|
||||
@ -160,41 +142,23 @@ static void write(uint8_t *buf, size_t nbytes)
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t readbyte_(void)
|
||||
uint8_t readbyte(void)
|
||||
{
|
||||
for (;;) {
|
||||
if (*can_rx) {
|
||||
uint32_t b = *rx;
|
||||
return b;
|
||||
return *rx;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t readbyte(uint8_t *mode, uint8_t *mode_bytes_left)
|
||||
{
|
||||
if (*mode_bytes_left == 0) {
|
||||
*mode = readbyte_();
|
||||
if (*mode != MODE_CDC) {
|
||||
htif_puts("We only support MODE_CDC\n");
|
||||
assert(1 == 2);
|
||||
} else {
|
||||
*mode_bytes_left = readbyte_();
|
||||
}
|
||||
}
|
||||
uint8_t b = readbyte_();
|
||||
*mode_bytes_left -= 1;
|
||||
return b;
|
||||
}
|
||||
|
||||
static int read(uint8_t *buf, size_t bufsize, size_t nbytes, uint8_t *mode,
|
||||
uint8_t *mode_bytes_left)
|
||||
static int read(uint8_t *buf, size_t bufsize, size_t nbytes)
|
||||
{
|
||||
if (nbytes > bufsize) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
for (int n = 0; n < nbytes; n++) {
|
||||
buf[n] = readbyte(mode, mode_bytes_left);
|
||||
buf[n] = readbyte();
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
@ -8,12 +8,6 @@
|
||||
#ifndef PROTO_H
|
||||
#define PROTO_H
|
||||
|
||||
enum mode {
|
||||
MODE_TKEYCTRL = 0x20,
|
||||
MODE_CDC = 0x40,
|
||||
MODE_HID = 0x80,
|
||||
};
|
||||
|
||||
enum endpoints {
|
||||
DST_HW_IFPGA,
|
||||
DST_HW_AFPGA,
|
||||
@ -58,8 +52,7 @@ struct frame_header {
|
||||
|
||||
/*@ -exportlocal @*/
|
||||
void writebyte(uint8_t b);
|
||||
uint8_t readbyte(uint8_t *mode, uint8_t *mode_bytes_left);
|
||||
uint8_t readbyte(void);
|
||||
void fwreply(struct frame_header hdr, enum fwcmd rspcode, uint8_t *buf);
|
||||
int readcommand(struct frame_header *hdr, uint8_t *cmd, int state,
|
||||
uint8_t *mode, uint8_t *mode_bytes_left);
|
||||
int readcommand(struct frame_header *hdr, uint8_t *cmd, int state);
|
||||
#endif
|
||||
|
||||
@ -82,8 +82,8 @@
|
||||
#define TK1_MMIO_TIMER_TIMER 0xc100002c
|
||||
|
||||
#define TK1_MMIO_UDS_BASE 0xc2000000
|
||||
#define TK1_MMIO_UDS_FIRST 0xc2000000
|
||||
#define TK1_MMIO_UDS_LAST 0xc200001c
|
||||
#define TK1_MMIO_UDS_FIRST 0xc2000040
|
||||
#define TK1_MMIO_UDS_LAST 0xc200005c
|
||||
|
||||
#define TK1_MMIO_UART_BASE 0xc3000000
|
||||
#define TK1_MMIO_UART_RX_STATUS 0xc3000080
|
||||
|
||||
@ -20,9 +20,6 @@ module application_fpga (
|
||||
output wire interface_rx,
|
||||
input wire interface_tx,
|
||||
|
||||
input wire interface_ch552_cts, // CH552 clear to send, 1 = OK, 0 = NOK
|
||||
output wire interface_fpga_cts, // FPGA clear to send, 1 = OK, 0 = NOK
|
||||
|
||||
output wire spi_ss,
|
||||
output wire spi_sck,
|
||||
output wire spi_mosi,
|
||||
@ -310,9 +307,6 @@ module application_fpga (
|
||||
.rxd(interface_tx),
|
||||
.txd(interface_rx),
|
||||
|
||||
.ch552_cts(interface_ch552_cts),
|
||||
.fpga_cts (interface_fpga_cts),
|
||||
|
||||
.cs(uart_cs),
|
||||
.we(uart_we),
|
||||
.address(uart_address),
|
||||
@ -430,7 +424,7 @@ module application_fpga (
|
||||
|
||||
ram_cs = 1'h0;
|
||||
ram_we = 4'h0;
|
||||
ram_address = cpu_addr[16 : 2];
|
||||
ram_address = cpu_addr[17 : 2];
|
||||
ram_write_data = cpu_wdata;
|
||||
|
||||
fw_ram_cs = 1'h0;
|
||||
|
||||
@ -33,9 +33,6 @@ module application_fpga_sim (
|
||||
output wire interface_rx,
|
||||
input wire interface_tx,
|
||||
|
||||
input wire interface_ch552_cts,
|
||||
output wire interface_fpga_cts,
|
||||
|
||||
output wire spi_ss,
|
||||
output wire spi_sck,
|
||||
output wire spi_mosi,
|
||||
@ -321,9 +318,6 @@ module application_fpga_sim (
|
||||
.rxd(interface_tx),
|
||||
.txd(interface_rx),
|
||||
|
||||
.ch552_cts(interface_ch552_cts),
|
||||
.fpga_cts (interface_fpga_cts),
|
||||
|
||||
.cs(uart_cs),
|
||||
.we(uart_we),
|
||||
.address(uart_address),
|
||||
@ -444,7 +438,7 @@ module application_fpga_sim (
|
||||
|
||||
ram_cs = 1'h0;
|
||||
ram_we = 4'h0;
|
||||
ram_address = cpu_addr[16 : 2];
|
||||
ram_address = cpu_addr[17 : 2];
|
||||
ram_write_data = cpu_wdata;
|
||||
|
||||
fw_ram_cs = 1'h0;
|
||||
|
||||
@ -315,7 +315,6 @@ int main(int argc, char **argv, char **env)
|
||||
uart_init(&u, &top.interface_tx, &top.interface_rx, BIT_DIV);
|
||||
|
||||
top.clk = 0;
|
||||
top.interface_ch552_cts = 1;
|
||||
|
||||
while (!Verilated::gotFinish()) {
|
||||
uint8_t to_host = 0;
|
||||
|
||||
@ -29,8 +29,6 @@ module tb_application_fpga_sim ();
|
||||
reg tb_clk = 0;
|
||||
wire tb_interface_rx;
|
||||
reg tb_interface_tx = 1'h1; // Set to 1 to simulate inactive UART
|
||||
reg tb_interface_ch552_cts = 1'h1; // Set to 1 to simulate OK to send
|
||||
reg tb_interface_fpga_cts;
|
||||
wire tb_spi_ss;
|
||||
wire tb_spi_sck;
|
||||
wire tb_spi_mosi;
|
||||
@ -51,8 +49,6 @@ module tb_application_fpga_sim ();
|
||||
.clk(tb_clk),
|
||||
.interface_rx(tb_interface_rx),
|
||||
.interface_tx(tb_interface_tx),
|
||||
.interface_ch552_cts(tb_interface_ch552_cts),
|
||||
.interface_fpga_cts(tb_interface_fpga_cts),
|
||||
.spi_ss(tb_spi_ss),
|
||||
.spi_sck(tb_spi_sck),
|
||||
.spi_mosi(tb_spi_mosi),
|
||||
|
||||
@ -3,6 +3,7 @@ TARGET = usb_device_cdc
|
||||
CH554_SDCC=~/ch554_sdcc/
|
||||
CHPROG=chprog
|
||||
|
||||
|
||||
# Adjust the XRAM location and size to leave space for the USB DMA buffers
|
||||
# Buffer layout in XRAM:
|
||||
# 0x0000 Ep0Buffer[8]
|
||||
@ -10,11 +11,8 @@ CHPROG=chprog
|
||||
# 0x0080 EP2Buffer[2*64]
|
||||
#
|
||||
# This takes a total of 256bytes, so there are 768 bytes left.
|
||||
#XRAM_SIZE = 0x0300
|
||||
#XRAM_LOC = 0x0100
|
||||
|
||||
XRAM_SIZE = 0x0400
|
||||
XRAM_LOC = 0x0000
|
||||
XRAM_SIZE = 0x0300
|
||||
XRAM_LOC = 0x0100
|
||||
|
||||
FREQ_SYS = 16000000
|
||||
|
||||
@ -23,8 +21,7 @@ usb_strings.h: encode_usb_strings.py
|
||||
|
||||
C_FILES = \
|
||||
main.c \
|
||||
include/debug.c \
|
||||
include/print.c
|
||||
include/debug.c
|
||||
|
||||
pre-flash:
|
||||
|
||||
|
||||
@ -8,8 +8,6 @@ WCHISP ?= wchisptool -g -f
|
||||
|
||||
#######################################################
|
||||
|
||||
EXTRA_FLAGS = -D BUILD_CODE
|
||||
|
||||
FREQ_SYS ?= 24000000
|
||||
|
||||
XRAM_SIZE ?= 0x0400
|
||||
|
||||
@ -37,17 +37,17 @@ if __name__ == "__main__":
|
||||
f.write('#ifndef USB_STRINGS\n')
|
||||
f.write('#define USB_STRINGS\n')
|
||||
|
||||
f.write('unsigned char __code ProdDesc[]={{ // "{}"\n'.format(product))
|
||||
f.write('unsigned char __code Prod_Des[]={{ // "{}"\n'.format(product))
|
||||
f.write(' ')
|
||||
f.write(', '.join(['0x{:02x}'.format(i) for i in string_to_descriptor(product)]))
|
||||
f.write('\n};\n\n')
|
||||
|
||||
f.write('unsigned char __code ManufDesc[]={{ // "{}"\n'.format(manufacturer))
|
||||
f.write('unsigned char __code Manuf_Des[]={{ // "{}"\n'.format(manufacturer))
|
||||
f.write(' ')
|
||||
f.write(', '.join(['0x{:02x}'.format(i) for i in string_to_descriptor(manufacturer)]))
|
||||
f.write('\n};\n\n')
|
||||
|
||||
f.write('unsigned char __code SerialDesc[]={{ // "{}"\n'.format(serial))
|
||||
f.write('unsigned char __code SerDes[]={{ // "{}"\n'.format(serial))
|
||||
f.write(' ')
|
||||
f.write(', '.join(['0x{:02x}'.format(i) for i in string_to_descriptor(serial)]))
|
||||
f.write('\n};\n\n')
|
||||
|
||||
@ -271,8 +271,8 @@ SFR(PIN_FUNC, 0xC6); // pin function selection
|
||||
#define bT2EX_PIN_X 0x02 // T2EX/CAP2 alternate pin enable: 0=T2EX/CAP2 on P1.1, 1=T2EX/CAP2 on RST
|
||||
#define bT2_PIN_X 0x01 // T2/CAP1 alternate pin enable: 0=T2/CAP1 on P1.1, 1=T2/CAP1 on P1.4
|
||||
SFR(XBUS_AUX, 0xA2); // xBUS auxiliary setting
|
||||
#define bUART0_TX 0x80 // ReadOnly: indicate UART0 transmit status
|
||||
#define bUART0_RX 0x40 // ReadOnly: indicate UART0 receive status
|
||||
#define bUART0_TX 0x80 // ReadOnly: indicate UART0 transmittal status
|
||||
#define bUART0_RX 0x40 // ReadOnly: indicate UART0 receiving status
|
||||
#define bSAFE_MOD_ACT 0x20 // ReadOnly: safe mode action status
|
||||
#define GF2 0x08 // general purpose flag bit 2
|
||||
#define bDPTR_AUTO_INC 0x04 // enable DPTR auto increase if finished MOVX_@DPTR instruction
|
||||
@ -325,20 +325,20 @@ SFR(SCON, 0x98); // UART0 control (serial port control)
|
||||
// 11 - mode 3, 9-bit UART, baud rate = variable by timer1 or timer2 overflow rate
|
||||
SBIT(SM2, 0x98, 5); // enable multi-device communication in mode 2/3
|
||||
#define MASK_UART0_MOD 0xE0 // bit mask of UART0 mode
|
||||
SBIT(REN, 0x98, 4); // enable UART0 receive
|
||||
SBIT(REN, 0x98, 4); // enable UART0 receiving
|
||||
SBIT(TB8, 0x98, 3); // the 9th transmitted data bit in mode 2/3
|
||||
SBIT(RB8, 0x98, 2); // 9th data bit received in mode 2/3, or stop bit received for mode 1
|
||||
SBIT(TI, 0x98, 1); // transmit interrupt flag, set by hardware after completion of a serial transmit, need software clear
|
||||
SBIT(RI, 0x98, 0); // receive interrupt flag, set by hardware after completion of a serial receive, need software clear
|
||||
SFR(SBUF, 0x99); // UART0 data buffer: reading for receive, writing for transmit
|
||||
SBIT(TI, 0x98, 1); // transmit interrupt flag, set by hardware after completion of a serial transmittal, need software clear
|
||||
SBIT(RI, 0x98, 0); // receive interrupt flag, set by hardware after completion of a serial receiving, need software clear
|
||||
SFR(SBUF, 0x99); // UART0 data buffer: reading for receiving, writing for transmittal
|
||||
|
||||
/* Timer2/Capture2 Registers */
|
||||
SFR(T2CON, 0xC8); // timer 2 control
|
||||
SBIT(TF2, 0xC8, 7); // timer2 overflow & interrupt flag, need software clear, the flag will not be set when either RCLK=1 or TCLK=1
|
||||
SBIT(CAP1F, 0xC8, 7); // timer2 capture 1 interrupt flag, set by T2 edge trigger if bT2_CAP1_EN=1, need software clear
|
||||
SBIT(EXF2, 0xC8, 6); // timer2 external flag, set by T2EX edge trigger if EXEN2=1, need software clear
|
||||
SBIT(RCLK, 0xC8, 5); // selection UART0 receive clock: 0=timer1 overflow pulse, 1=timer2 overflow pulse
|
||||
SBIT(TCLK, 0xC8, 4); // selection UART0 transmit clock: 0=timer1 overflow pulse, 1=timer2 overflow pulse
|
||||
SBIT(RCLK, 0xC8, 5); // selection UART0 receiving clock: 0=timer1 overflow pulse, 1=timer2 overflow pulse
|
||||
SBIT(TCLK, 0xC8, 4); // selection UART0 transmittal clock: 0=timer1 overflow pulse, 1=timer2 overflow pulse
|
||||
SBIT(EXEN2, 0xC8, 3); // enable T2EX trigger function: 0=ignore T2EX, 1=trigger reload or capture by T2EX edge
|
||||
SBIT(TR2, 0xC8, 2); // timer2 run enable
|
||||
SBIT(C_T2, 0xC8, 1); // timer2 clock source selection: 0=timer base internal clock, 1=external edge counter base T2 falling edge
|
||||
@ -389,7 +389,7 @@ SFR(SPI0_STAT, 0xF8); // SPI 0 status
|
||||
SBIT(S0_FREE, 0xF8, 3); // ReadOnly: SPI0 free status
|
||||
SBIT(S0_T_FIFO, 0xF8, 2); // ReadOnly: tx FIFO count for SPI0
|
||||
SBIT(S0_R_FIFO, 0xF8, 0); // ReadOnly: rx FIFO count for SPI0
|
||||
SFR(SPI0_DATA, 0xF9); // FIFO data port: reading for receive, writing for transmit
|
||||
SFR(SPI0_DATA, 0xF9); // FIFO data port: reading for receiving, writing for transmittal
|
||||
SFR(SPI0_CTRL, 0xFA); // SPI 0 control
|
||||
#define bS0_MISO_OE 0x80 // SPI0 MISO output enable
|
||||
#define bS0_MOSI_OE 0x40 // SPI0 MOSI output enable
|
||||
@ -415,12 +415,12 @@ SFR(SPI0_SETUP, 0xFC); // SPI 0 setup
|
||||
SFR(SCON1, 0xC0); // UART1 control (serial port control)
|
||||
SBIT(U1SM0, 0xC0, 7); // UART1 mode, selection data bit: 0=8 bits data, 1=9 bits data
|
||||
SBIT(U1SMOD, 0xC0, 5); // UART1 2X baud rate selection: 0=slow(Fsys/32/(256-SBAUD1)), 1=fast(Fsys/16/(256-SBAUD1))
|
||||
SBIT(U1REN, 0xC0, 4); // enable UART1 receive
|
||||
SBIT(U1REN, 0xC0, 4); // enable UART1 receiving
|
||||
SBIT(U1TB8, 0xC0, 3); // the 9th transmitted data bit in 9 bits data mode
|
||||
SBIT(U1RB8, 0xC0, 2); // 9th data bit received in 9 bits data mode, or stop bit received for 8 bits data mode
|
||||
SBIT(U1TI, 0xC0, 1); // transmit interrupt flag, set by hardware after completion of a serial transmit, need software clear
|
||||
SBIT(U1RI, 0xC0, 0); // receive interrupt flag, set by hardware after completion of a serial receive, need software clear
|
||||
SFR(SBUF1, 0xC1); // UART1 data buffer: reading for receive, writing for transmit
|
||||
SBIT(U1TI, 0xC0, 1); // transmit interrupt flag, set by hardware after completion of a serial transmittal, need software clear
|
||||
SBIT(U1RI, 0xC0, 0); // receive interrupt flag, set by hardware after completion of a serial receiving, need software clear
|
||||
SFR(SBUF1, 0xC1); // UART1 data buffer: reading for receiving, writing for transmittal
|
||||
SFR(SBAUD1, 0xC2); // UART1 baud rate setting
|
||||
|
||||
/* ADC and comparator Registers */
|
||||
@ -495,38 +495,38 @@ SFR(UDEV_CTRL, 0xD1); // USB device physical port control
|
||||
#define bUH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset
|
||||
#define bUH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
|
||||
SFR(UEP1_CTRL, 0xD2); // endpoint 1 control
|
||||
#define bUEP_R_TOG 0x80 // expected data toggle flag of USB endpoint X receive (OUT): 0=DATA0, 1=DATA1
|
||||
#define bUEP_T_TOG 0x40 // prepared data toggle flag of USB endpoint X transmit (IN): 0=DATA0, 1=DATA1
|
||||
#define bUEP_R_TOG 0x80 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
|
||||
#define bUEP_T_TOG 0x40 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
|
||||
#define bUEP_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
|
||||
#define bUEP_R_RES1 0x08 // handshake response type high bit for USB endpoint X receive (OUT)
|
||||
#define bUEP_R_RES0 0x04 // handshake response type low bit for USB endpoint X receive (OUT)
|
||||
#define MASK_UEP_R_RES 0x0C // bit mask of handshake response type for USB endpoint X receive (OUT)
|
||||
#define bUEP_R_RES1 0x08 // handshake response type high bit for USB endpoint X receiving (OUT)
|
||||
#define bUEP_R_RES0 0x04 // handshake response type low bit for USB endpoint X receiving (OUT)
|
||||
#define MASK_UEP_R_RES 0x0C // bit mask of handshake response type for USB endpoint X receiving (OUT)
|
||||
#define UEP_R_RES_ACK 0x00
|
||||
#define UEP_R_RES_TOUT 0x04
|
||||
#define UEP_R_RES_NAK 0x08
|
||||
#define UEP_R_RES_STALL 0x0C
|
||||
// bUEP_R_RES1 & bUEP_R_RES0: handshake response type for USB endpoint X receive (OUT)
|
||||
// bUEP_R_RES1 & bUEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
|
||||
// 00: ACK (ready)
|
||||
// 01: no response, time out to host, for non-zero endpoint isochronous transactions
|
||||
// 10: NAK (busy)
|
||||
// 11: STALL (error)
|
||||
#define bUEP_T_RES1 0x02 // handshake response type high bit for USB endpoint X transmit (IN)
|
||||
#define bUEP_T_RES0 0x01 // handshake response type low bit for USB endpoint X transmit (IN)
|
||||
#define MASK_UEP_T_RES 0x03 // bit mask of handshake response type for USB endpoint X transmit (IN)
|
||||
#define bUEP_T_RES1 0x02 // handshake response type high bit for USB endpoint X transmittal (IN)
|
||||
#define bUEP_T_RES0 0x01 // handshake response type low bit for USB endpoint X transmittal (IN)
|
||||
#define MASK_UEP_T_RES 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN)
|
||||
#define UEP_T_RES_ACK 0x00
|
||||
#define UEP_T_RES_TOUT 0x01
|
||||
#define UEP_T_RES_NAK 0x02
|
||||
#define UEP_T_RES_STALL 0x03
|
||||
// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmit (IN)
|
||||
// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
|
||||
// 00: DATA0 or DATA1 then expecting ACK (ready)
|
||||
// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
|
||||
// 10: NAK (busy)
|
||||
// 11: STALL (error)
|
||||
SFR(UEP1_T_LEN, 0xD3); // endpoint 1 transmit length
|
||||
SFR(UEP1_T_LEN, 0xD3); // endpoint 1 transmittal length
|
||||
SFR(UEP2_CTRL, 0xD4); // endpoint 2 control
|
||||
SFR(UEP2_T_LEN, 0xD5); // endpoint 2 transmit length
|
||||
SFR(UEP2_T_LEN, 0xD5); // endpoint 2 transmittal length
|
||||
SFR(UEP3_CTRL, 0xD6); // endpoint 3 control
|
||||
SFR(UEP3_T_LEN, 0xD7); // endpoint 3 transmit length
|
||||
SFR(UEP3_T_LEN, 0xD7); // endpoint 3 transmittal length
|
||||
SFR(USB_INT_FG, 0xD8); // USB interrupt flag
|
||||
SBIT(U_IS_NAK, 0xD8, 7); // ReadOnly: indicate current USB transfer is NAK received
|
||||
SBIT(U_TOG_OK, 0xD8, 6); // ReadOnly: indicate current USB transfer toggle is OK
|
||||
@ -558,16 +558,16 @@ SFR(USB_MIS_ST, 0xDA); // ReadOnly: USB miscellaneous status
|
||||
#define bUMS_SOF_PRES 0x80 // ReadOnly: indicate host SOF timer presage status
|
||||
#define bUMS_SOF_ACT 0x40 // ReadOnly: indicate host SOF timer action status for USB host
|
||||
#define bUMS_SIE_FREE 0x20 // ReadOnly: indicate USB SIE free status
|
||||
#define bUMS_R_FIFO_RDY 0x10 // ReadOnly: indicate USB receive FIFO ready status (not empty)
|
||||
#define bUMS_R_FIFO_RDY 0x10 // ReadOnly: indicate USB receiving FIFO ready status (not empty)
|
||||
#define bUMS_BUS_RESET 0x08 // ReadOnly: indicate USB bus reset status
|
||||
#define bUMS_SUSPEND 0x04 // ReadOnly: indicate USB suspend status
|
||||
#define bUMS_DM_LEVEL 0x02 // ReadOnly: indicate UDM level saved at device attached to USB host
|
||||
#define bUMS_DEV_ATTACH 0x01 // ReadOnly: indicate device attached status on USB host
|
||||
SFR(USB_RX_LEN, 0xDB); // ReadOnly: USB receive length
|
||||
SFR(USB_RX_LEN, 0xDB); // ReadOnly: USB receiving length
|
||||
SFR(UEP0_CTRL, 0xDC); // endpoint 0 control
|
||||
SFR(UEP0_T_LEN, 0xDD); // endpoint 0 transmit length
|
||||
SFR(UEP0_T_LEN, 0xDD); // endpoint 0 transmittal length
|
||||
SFR(UEP4_CTRL, 0xDE); // endpoint 4 control
|
||||
SFR(UEP4_T_LEN, 0xDF); // endpoint 4 transmit length
|
||||
SFR(UEP4_T_LEN, 0xDF); // endpoint 4 transmittal length
|
||||
SFR(USB_INT_EN, 0xE1); // USB interrupt enable
|
||||
#define bUIE_DEV_SOF 0x80 // enable interrupt for SOF received for USB device mode
|
||||
#define bUIE_DEV_NAK 0x40 // enable interrupt for NAK responded for USB device mode
|
||||
@ -606,31 +606,31 @@ SFR16(UEP3_DMA, 0xE6); // endpoint 3 buffer start address, little-endian
|
||||
SFR(UEP3_DMA_L, 0xE6); // endpoint 3 buffer start address low byte
|
||||
SFR(UEP3_DMA_H, 0xE7); // endpoint 3 buffer start address high byte
|
||||
SFR(UEP4_1_MOD, 0xEA); // endpoint 4/1 mode
|
||||
#define bUEP1_RX_EN 0x80 // enable USB endpoint 1 receive (OUT)
|
||||
#define bUEP1_TX_EN 0x40 // enable USB endpoint 1 transmit (IN)
|
||||
#define bUEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT)
|
||||
#define bUEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN)
|
||||
#define bUEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1
|
||||
// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA
|
||||
// 0 0 x: disable endpoint and disable buffer
|
||||
// 1 0 0: 64 bytes buffer for receive (OUT endpoint)
|
||||
// 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receive (OUT endpoint), total=128bytes
|
||||
// 0 1 0: 64 bytes buffer for transmit (IN endpoint)
|
||||
// 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmit (IN endpoint), total=128bytes
|
||||
// 1 1 0: 64 bytes buffer for receive (OUT endpoint) + 64 bytes buffer for transmit (IN endpoint), total=128bytes
|
||||
// 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receive (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmit (IN endpoint), total=256bytes
|
||||
#define bUEP4_RX_EN 0x08 // enable USB endpoint 4 receive (OUT)
|
||||
#define bUEP4_TX_EN 0x04 // enable USB endpoint 4 transmit (IN)
|
||||
// 1 0 0: 64 bytes buffer for receiving (OUT endpoint)
|
||||
// 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes
|
||||
// 0 1 0: 64 bytes buffer for transmittal (IN endpoint)
|
||||
// 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes
|
||||
// 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes
|
||||
// 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes
|
||||
#define bUEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT)
|
||||
#define bUEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN)
|
||||
// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA
|
||||
// 0 0: single 64 bytes buffer for endpoint 0 receive & transmit (OUT & IN endpoint)
|
||||
// 1 0: single 64 bytes buffer for endpoint 0 receive & transmit (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receive (OUT endpoint), total=128bytes
|
||||
// 0 1: single 64 bytes buffer for endpoint 0 receive & transmit (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmit (IN endpoint), total=128bytes
|
||||
// 1 1: single 64 bytes buffer for endpoint 0 receive & transmit (OUT & IN endpoint)
|
||||
// + 64 bytes buffer for endpoint 4 receive (OUT endpoint) + 64 bytes buffer for endpoint 4 transmit (IN endpoint), total=192bytes
|
||||
// 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
|
||||
// 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes
|
||||
// 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes
|
||||
// 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
|
||||
// + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes
|
||||
SFR(UEP2_3_MOD, 0xEB); // endpoint 2/3 mode
|
||||
#define bUEP3_RX_EN 0x80 // enable USB endpoint 3 receive (OUT)
|
||||
#define bUEP3_TX_EN 0x40 // enable USB endpoint 3 transmit (IN)
|
||||
#define bUEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT)
|
||||
#define bUEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN)
|
||||
#define bUEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3
|
||||
#define bUEP2_RX_EN 0x08 // enable USB endpoint 2 receive (OUT)
|
||||
#define bUEP2_TX_EN 0x04 // enable USB endpoint 2 transmit (IN)
|
||||
#define bUEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT)
|
||||
#define bUEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN)
|
||||
#define bUEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2
|
||||
SFR16(UEP0_DMA, 0xEC); // endpoint 0 buffer start address, little-endian
|
||||
SFR(UEP0_DMA_L, 0xEC); // endpoint 0 buffer start address low byte
|
||||
@ -644,34 +644,34 @@ SFR(UEP1_DMA_H, 0xEF); // endpoint 1 buffer start address high byte
|
||||
#define bUH_SOF_EN 0x40 // USB host automatic SOF enable
|
||||
//sfr UH_RX_CTRL = 0xD4; // host receiver endpoint control
|
||||
#define UH_RX_CTRL UEP2_CTRL
|
||||
#define bUH_R_TOG 0x80 // expected data toggle flag of host receive (IN): 0=DATA0, 1=DATA1
|
||||
#define bUH_R_TOG 0x80 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
|
||||
#define bUH_R_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
|
||||
#define bUH_R_RES 0x04 // prepared handshake response type for host receive (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
|
||||
#define bUH_R_RES 0x04 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
|
||||
//sfr UH_EP_PID = 0xD5; // host endpoint and token PID, lower 4 bits for endpoint number, upper 4 bits for token PID
|
||||
#define UH_EP_PID UEP2_T_LEN
|
||||
#define MASK_UH_TOKEN 0xF0 // bit mask of token PID for USB host transfer
|
||||
#define MASK_UH_ENDP 0x0F // bit mask of endpoint number for USB host transfer
|
||||
//sfr UH_TX_CTRL = 0xD6; // host transmit endpoint control
|
||||
//sfr UH_TX_CTRL = 0xD6; // host transmittal endpoint control
|
||||
#define UH_TX_CTRL UEP3_CTRL
|
||||
#define bUH_T_TOG 0x40 // prepared data toggle flag of host transmit (SETUP/OUT): 0=DATA0, 1=DATA1
|
||||
#define bUH_T_TOG 0x40 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
|
||||
#define bUH_T_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
|
||||
#define bUH_T_RES 0x01 // expected handshake response type for host transmit (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
|
||||
//sfr UH_TX_LEN = 0xD7; // host transmit endpoint transmit length
|
||||
#define bUH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
|
||||
//sfr UH_TX_LEN = 0xD7; // host transmittal endpoint transmittal length
|
||||
#define UH_TX_LEN UEP3_T_LEN
|
||||
//sfr UH_EP_MOD = 0xEB; // host endpoint mode
|
||||
#define UH_EP_MOD UEP2_3_MOD
|
||||
#define bUH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmit
|
||||
#define bUH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal
|
||||
#define bUH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint
|
||||
// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA
|
||||
// 0 x: disable endpoint and disable buffer
|
||||
// 1 0: 64 bytes buffer for transmit (OUT endpoint)
|
||||
// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmit (OUT endpoint), total=128bytes
|
||||
#define bUH_EP_RX_EN 0x08 // enable USB host IN endpoint receive
|
||||
// 1 0: 64 bytes buffer for transmittal (OUT endpoint)
|
||||
// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes
|
||||
#define bUH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving
|
||||
#define bUH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint
|
||||
// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA
|
||||
// 0 x: disable endpoint and disable buffer
|
||||
// 1 0: 64 bytes buffer for receive (IN endpoint)
|
||||
// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receive (IN endpoint), total=128bytes
|
||||
// 1 0: 64 bytes buffer for receiving (IN endpoint)
|
||||
// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes
|
||||
//sfr16 UH_RX_DMA = 0xE4; // host rx endpoint buffer start address, little-endian
|
||||
#define UH_RX_DMA UEP2_DMA
|
||||
//sfr UH_RX_DMA_L = 0xE4; // host rx endpoint buffer start address low byte
|
||||
|
||||
@ -11,8 +11,6 @@ Header file for CH554 microcontrollers.
|
||||
#ifndef __USB_DEF__
|
||||
#define __USB_DEF__
|
||||
|
||||
#include "mem.h"
|
||||
|
||||
/*----- USB constant and structure define --------------------------------*/
|
||||
|
||||
/* USB PID */
|
||||
@ -55,41 +53,34 @@ Header file for CH554 microcontrollers.
|
||||
#define HUB_SET_DESCRIPTOR 0x07
|
||||
#endif
|
||||
|
||||
/* USB HID class request code */
|
||||
#ifndef HID_GET_REPORT
|
||||
#define HID_GET_REPORT 0x01
|
||||
#define HID_GET_IDLE 0x02
|
||||
#define HID_GET_PROTOCOL 0x03
|
||||
#define HID_SET_REPORT 0x09
|
||||
#define HID_SET_IDLE 0x0A
|
||||
#define HID_SET_PROTOCOL 0x0B
|
||||
#endif
|
||||
|
||||
/* Bit define for USB request type */
|
||||
#ifndef USB_REQ_TYPE_MASK
|
||||
#define USB_REQ_TYPE_IN 0x80 /* Control IN, device to host */
|
||||
#define USB_REQ_TYPE_OUT 0x00 /* Control OUT, host to device */
|
||||
#define USB_REQ_TYPE_READ 0x80 /* Control read, device to host */
|
||||
#define USB_REQ_TYPE_WRITE 0x00 /* Control write, host to device */
|
||||
#define USB_REQ_TYPE_MASK 0x60 /* Bit mask of request type */
|
||||
#define USB_REQ_TYPE_STANDARD 0x00
|
||||
#define USB_REQ_TYPE_CLASS 0x20
|
||||
#define USB_REQ_TYPE_VENDOR 0x40
|
||||
#define USB_REQ_TYPE_RESERVED 0x60
|
||||
#define USB_REQ_RECIP_MASK 0x1F /* Bit mask of request recipient */
|
||||
#ifndef USB_REQ_TYP_MASK
|
||||
#define USB_REQ_TYP_IN 0x80 /* control IN, device to host */
|
||||
#define USB_REQ_TYP_OUT 0x00 /* control OUT, host to device */
|
||||
#define USB_REQ_TYP_READ 0x80 /* control read, device to host */
|
||||
#define USB_REQ_TYP_WRITE 0x00 /* control write, host to device */
|
||||
#define USB_REQ_TYP_MASK 0x60 /* bit mask of request type */
|
||||
#define USB_REQ_TYP_STANDARD 0x00
|
||||
#define USB_REQ_TYP_CLASS 0x20
|
||||
#define USB_REQ_TYP_VENDOR 0x40
|
||||
#define USB_REQ_TYP_RESERVED 0x60
|
||||
#define USB_REQ_RECIP_MASK 0x1F /* bit mask of request recipient */
|
||||
#define USB_REQ_RECIP_DEVICE 0x00
|
||||
#define USB_REQ_RECIP_INTERF 0x01
|
||||
#define USB_REQ_RECIP_ENDP 0x02
|
||||
#define USB_REQ_RECIP_OTHER 0x03
|
||||
#endif
|
||||
|
||||
/* USB HID class request code */
|
||||
#ifndef USB_HID_REQ_TYPE
|
||||
#define USB_HID_REQ_TYPE_GET_REPORT 0x01
|
||||
#define USB_HID_REQ_TYPE_GET_IDLE 0x02
|
||||
#define USB_HID_REQ_TYPE_GET_PROTOCOL 0x03
|
||||
#define USB_HID_REQ_TYPE_SET_REPORT 0x09
|
||||
#define USB_HID_REQ_TYPE_SET_IDLE 0x0A
|
||||
#define USB_HID_REQ_TYPE_SET_PROTOCOL 0x0B
|
||||
#endif
|
||||
|
||||
/* USB CDC class request code */
|
||||
#ifndef USB_CDC_REQ_TYPE
|
||||
#define USB_CDC_REQ_TYPE_SET_LINE_CODING 0x20
|
||||
#define USB_CDC_REQ_TYPE_GET_LINE_CODING 0x21
|
||||
#define USB_CDC_REQ_TYPE_SET_CONTROL_LINE_STATE 0x22
|
||||
#endif
|
||||
|
||||
/* USB request type for hub class request */
|
||||
#ifndef HUB_GET_HUB_DESCRIPTOR
|
||||
#define HUB_CLEAR_HUB_FEATURE 0x20
|
||||
@ -122,112 +113,78 @@ Header file for CH554 microcontrollers.
|
||||
#endif
|
||||
|
||||
/* USB descriptor type */
|
||||
#ifndef USB_DESC_TYPE_DEVICE
|
||||
#define USB_DESC_TYPE_DEVICE 0x01 // USB 1.1
|
||||
#define USB_DESC_TYPE_CONFIGURATION 0x02 // USB 1.1
|
||||
#define USB_DESC_TYPE_STRING 0x03 // USB 1.1
|
||||
#define USB_DESC_TYPE_INTERFACE 0x04 // USB 1.1
|
||||
#define USB_DESC_TYPE_ENDPOINT 0x05 // USB 1.1
|
||||
#define USB_DESC_TYPE_DEVICE_QUALIFIER 0x06 // USB 2.0
|
||||
#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 0x07 // USB 2.0
|
||||
#define USB_DESC_TYPE_INTERFACE_POWER 0x08 // USB 2.0
|
||||
#define USB_DESC_TYPE_OTG 0x09 // USB 2.0
|
||||
#define USB_DESC_TYPE_DEBUG 0x0A // USB 2.0
|
||||
#define USB_DESC_TYPE_INTERFACE_ASSOCIATION 0x0B // USB 2.0
|
||||
#define USB_DESC_TYPE_BOS 0x0F // USB 3.x (Binary Object Store)
|
||||
#define USB_DESC_TYPE_DEVICE_CAPABILITY 0x10 // USB 3.x
|
||||
#define USB_DESC_TYPE_HID 0x21 // HID 1.11
|
||||
#define USB_DESC_TYPE_REPORT 0x22 // HID 1.11
|
||||
#define USB_DESC_TYPE_PHYSICAL 0x23 // HID 1.11
|
||||
#define USB_DESC_TYPE_CS_INTERFACE 0x24 // Class-Specific (Audio, HID, CDC, etc.)
|
||||
#define USB_DESC_TYPE_CS_ENDPOINT 0x25 // Class-Specific (Audio, Not HID normally, CDC, etc.)
|
||||
#define USB_DESC_TYPE_SUPERSPEED_USB_ENDPOINT_COMPANION 0x30 // USB 3.x
|
||||
#define USB_DESC_TYPE_SUPERSPEEDPLUS_ISOCHRONOUS_ENDPOINT_COMPANION 0x31 // USB 3.x
|
||||
#ifndef USB_DESCR_TYP_DEVICE
|
||||
#define USB_DESCR_TYP_DEVICE 0x01
|
||||
#define USB_DESCR_TYP_CONFIG 0x02
|
||||
#define USB_DESCR_TYP_STRING 0x03
|
||||
#define USB_DESCR_TYP_INTERF 0x04
|
||||
#define USB_DESCR_TYP_ENDP 0x05
|
||||
#define USB_DESCR_TYP_QUALIF 0x06
|
||||
#define USB_DESCR_TYP_SPEED 0x07
|
||||
#define USB_DESCR_TYP_OTG 0x09
|
||||
#define USB_DESCR_TYP_HID 0x21
|
||||
#define USB_DESCR_TYP_REPORT 0x22
|
||||
#define USB_DESCR_TYP_PHYSIC 0x23
|
||||
#define USB_DESCR_TYP_CS_INTF 0x24
|
||||
#define USB_DESCR_TYP_CS_ENDP 0x25
|
||||
#define USB_DESCR_TYP_HUB 0x29
|
||||
#endif
|
||||
|
||||
/* USB device class */
|
||||
#ifndef USB_DEV_CLASS
|
||||
// Descriptor Usage; Description ; Examples
|
||||
#define USB_DEV_CLASS_RESERVED 0x00 // Device ; Unspecified ; Device class is unspecified, interface descriptors are used to determine needed drivers
|
||||
#define USB_DEV_CLASS_AUDIO 0x01 // Interface ; Audio ; Speaker, microphone, sound card, MIDI
|
||||
#define USB_DEV_CLASS_CDC_CONTROL 0x02 // Both ; Communications and CDC control ; UART and RS-232 serial adapter, modem, Wi-Fi adapter, Ethernet adapter. Used together with class 0Ah (CDC-Data) below
|
||||
#define USB_DEV_CLASS_HID 0x03 // Interface ; Human interface device (HID) ; Keyboard, mouse, joystick
|
||||
#define USB_DEV_CLASS_PHYSICAL 0x05 // Interface ; Physical interface device (PID) ; Force feedback joystick
|
||||
#define USB_DEV_CLASS_IMAGE 0x06 // Interface ; Media (PTP/MTP) ; Scanner, Camera
|
||||
#define USB_DEV_CLASS_PRINTER 0x07 // Interface ; Printer ; Laser printer, inkjet printer, CNC machine
|
||||
#define USB_DEV_CLASS_MASS_STORAGE 0x08 // Interface ; USB mass storage, USB Attached SCSI ; USB flash drive, memory card reader, digital audio player, digital camera, external drive
|
||||
#define USB_DEV_CLASS_HUB 0x09 // Device ; USB hub ; High speed USB hub
|
||||
#define USB_DEV_CLASS_CDC_DATA 0x0A // Interface ; CDC-Data ; Used together with class 02h (Communications and CDC Control) above
|
||||
#define USB_DEV_CLASS_SMART_CARD 0x0B // Interface ; Smart card ; USB smart card reader
|
||||
#define USB_DEV_CLASS_CONTENT_SECURITY 0x0D // Interface ; Content security ; Fingerprint reader
|
||||
#define USB_DEV_CLASS_VIDEO 0x0E // Interface ; Video ; Webcam
|
||||
#define USB_DEV_CLASS_PERSONAL_HEALTHCARE 0x0F // Interface ; Personal healthcare device class (PHDC) ; Pulse monitor (watch)
|
||||
#define USB_DEV_CLASS_AUDIO_VIDEO DEVICES 0x10 // Interface ; Audio/Video (AV) ; Webcam, TV
|
||||
#define USB_DEV_CLASS_BILLBOARD 0x11 // Device ; Billboard ; Describes USB-C alternate modes supported by device
|
||||
#define USB_DEV_CLASS_USB_TYPE_C_BRIDGE 0x12 // Interface ; ;
|
||||
#define USB_DEV_CLASS_USB_BULK_DISPLAY 0x13 // Interface ; ;
|
||||
#define USB_DEV_CLASS_MCTP_OVER_USB 0x14 // Interface ; ;
|
||||
#define USB_DEV_CLASS_I3C_DEVICE_CLASS 0x3C // Interface ; ;
|
||||
#define USB_DEV_CLASS_DIAGNOSTIC_DEVICE 0xDC // Both ; Diagnostic device ; USB compliance testing device
|
||||
#define USB_DEV_CLASS_WIRELESS_CONTROLLER 0xE0 // Interface ; Wireless Controller ; Bluetooth adapter, Microsoft RNDIS
|
||||
#define USB_DEV_CLASS_MISCELLANEOUS 0xEF // Both ; Miscellaneous ; ActiveSync device
|
||||
#define USB_DEV_CLASS_APPLICATION_SPECIFIC 0xFE // Interface ; Application-specific ; IrDA Bridge, Test & Measurement Class (USBTMC), USB DFU (Device Firmware Upgrade)
|
||||
#define USB_DEV_CLASS_VENDOR_SPECIFIC 0xFF // Both ; Vendor-specific ; Indicates that a device needs vendor-specific drivers
|
||||
#ifndef USB_DEV_CLASS_HUB
|
||||
#define USB_DEV_CLASS_RESERVED 0x00
|
||||
#define USB_DEV_CLASS_AUDIO 0x01
|
||||
#define USB_DEV_CLASS_COMMUNIC 0x02
|
||||
#define USB_DEV_CLASS_HID 0x03
|
||||
#define USB_DEV_CLASS_MONITOR 0x04
|
||||
#define USB_DEV_CLASS_PHYSIC_IF 0x05
|
||||
#define USB_DEV_CLASS_POWER 0x06
|
||||
#define USB_DEV_CLASS_PRINTER 0x07
|
||||
#define USB_DEV_CLASS_STORAGE 0x08
|
||||
#define USB_DEV_CLASS_HUB 0x09
|
||||
#define USB_DEV_CLASS_VEN_SPEC 0xFF
|
||||
#endif
|
||||
|
||||
/* USB endpoint type and attributes */
|
||||
#ifndef USB_EP_TYPE_MASK
|
||||
#define USB_EP_TYPE_CONTROL 0x00
|
||||
#define USB_EP_TYPE_ISOCHRONOUS 0x01
|
||||
#define USB_EP_TYPE_BULK 0x02
|
||||
#define USB_EP_TYPE_INTERRUPT 0x03
|
||||
|
||||
#define USB_EP_DIR_MASK 0x80
|
||||
#define USB_EP_ADDR_MASK 0x0F
|
||||
#define USB_EP_TYPE_MASK 0x03
|
||||
#endif
|
||||
|
||||
/* USB string index */
|
||||
#ifndef USB_IDX_STR
|
||||
#define USB_IDX_LANGID_STR 0x00
|
||||
#define USB_IDX_MFC_STR 0x01
|
||||
#define USB_IDX_PRODUCT_STR 0x02
|
||||
#define USB_IDX_SERIAL_STR 0x03
|
||||
#define USB_IDX_INTERFACE_CDC_CTRL_STR 0x04
|
||||
#define USB_IDX_INTERFACE_CDC_DATA_STR 0x05
|
||||
#define USB_IDX_INTERFACE_FIDO_HID_STR 0x06
|
||||
#define USB_IDX_INTERFACE_TKEY_CTRL_STR 0x07
|
||||
#ifndef USB_ENDP_TYPE_MASK
|
||||
#define USB_ENDP_DIR_MASK 0x80
|
||||
#define USB_ENDP_ADDR_MASK 0x0F
|
||||
#define USB_ENDP_TYPE_MASK 0x03
|
||||
#define USB_ENDP_TYPE_CTRL 0x00
|
||||
#define USB_ENDP_TYPE_ISOCH 0x01
|
||||
#define USB_ENDP_TYPE_BULK 0x02
|
||||
#define USB_ENDP_TYPE_INTER 0x03
|
||||
#endif
|
||||
|
||||
#ifndef USB_DEVICE_ADDR
|
||||
#define USB_DEVICE_ADDR 0x02
|
||||
#define USB_DEVICE_ADDR 0x02 /* 默认的USB设备地址 */
|
||||
#endif
|
||||
#ifndef DEFAULT_EP0_SIZE
|
||||
#define DEFAULT_EP0_SIZE 64 /* Default maximum packet size for Endpoint 0 */
|
||||
#ifndef DEFAULT_ENDP0_SIZE
|
||||
#define DEFAULT_ENDP0_SIZE 8 /* default maximum packet size for endpoint 0 */
|
||||
#endif
|
||||
#ifndef DEFAULT_EP1_SIZE
|
||||
#define DEFAULT_EP1_SIZE 8 /* Default maximum packet size for Endpoint 1 */
|
||||
#ifndef DEFAULT_ENDP1_SIZE
|
||||
#define DEFAULT_ENDP1_SIZE 8 /* default maximum packet size for endpoint 1 */
|
||||
#endif
|
||||
#ifndef MAX_PACKET_SIZE
|
||||
#define MAX_PACKET_SIZE 64 /* Maximum packet size */
|
||||
#define MAX_PACKET_SIZE 64 /* maximum packet size */
|
||||
#endif
|
||||
#ifndef USB_BO_CBW_SIZE
|
||||
#define USB_BO_CBW_SIZE 0x1F
|
||||
#define USB_BO_CSW_SIZE 0x0D
|
||||
#define USB_BO_CBW_SIZE 0x1F /* 命令块CBW的总长度 */
|
||||
#define USB_BO_CSW_SIZE 0x0D /* 命令状态块CSW的总长度 */
|
||||
#endif
|
||||
#ifndef USB_BO_CBW_SIG0
|
||||
#define USB_BO_CBW_SIG0 0x55
|
||||
#define USB_BO_CBW_SIG0 0x55 /* 命令块CBW识别标志'USBC' */
|
||||
#define USB_BO_CBW_SIG1 0x53
|
||||
#define USB_BO_CBW_SIG2 0x42
|
||||
#define USB_BO_CBW_SIG3 0x43
|
||||
#define USB_BO_CSW_SIG0 0x55
|
||||
#define USB_BO_CSW_SIG0 0x55 /* 命令状态块CSW识别标志'USBS' */
|
||||
#define USB_BO_CSW_SIG1 0x53
|
||||
#define USB_BO_CSW_SIG2 0x42
|
||||
#define USB_BO_CSW_SIG3 0x53
|
||||
#endif
|
||||
|
||||
typedef struct _USB_SETUP_REQ {
|
||||
uint8_t bmRequestType;
|
||||
uint8_t bRequestType;
|
||||
uint8_t bRequest;
|
||||
uint8_t wValueL;
|
||||
uint8_t wValueH;
|
||||
@ -237,7 +194,7 @@ typedef struct _USB_SETUP_REQ {
|
||||
uint8_t wLengthH;
|
||||
} USB_SETUP_REQ, *PUSB_SETUP_REQ;
|
||||
|
||||
typedef USB_SETUP_REQ XDATA *PXUSB_SETUP_REQ;
|
||||
typedef USB_SETUP_REQ __xdata *PXUSB_SETUP_REQ;
|
||||
|
||||
typedef struct _USB_DEVICE_DESCR {
|
||||
uint8_t bLength;
|
||||
@ -260,7 +217,7 @@ typedef struct _USB_DEVICE_DESCR {
|
||||
uint8_t bNumConfigurations;
|
||||
} USB_DEV_DESCR, *PUSB_DEV_DESCR;
|
||||
|
||||
typedef USB_DEV_DESCR XDATA *PXUSB_DEV_DESCR;
|
||||
typedef USB_DEV_DESCR __xdata *PXUSB_DEV_DESCR;
|
||||
|
||||
typedef struct _USB_CONFIG_DESCR {
|
||||
uint8_t bLength;
|
||||
@ -274,7 +231,7 @@ typedef struct _USB_CONFIG_DESCR {
|
||||
uint8_t MaxPower;
|
||||
} USB_CFG_DESCR, *PUSB_CFG_DESCR;
|
||||
|
||||
typedef USB_CFG_DESCR XDATA *PXUSB_CFG_DESCR;
|
||||
typedef USB_CFG_DESCR __xdata *PXUSB_CFG_DESCR;
|
||||
|
||||
typedef struct _USB_INTERF_DESCR {
|
||||
uint8_t bLength;
|
||||
@ -288,7 +245,7 @@ typedef struct _USB_INTERF_DESCR {
|
||||
uint8_t iInterface;
|
||||
} USB_ITF_DESCR, *PUSB_ITF_DESCR;
|
||||
|
||||
typedef USB_ITF_DESCR XDATA *PXUSB_ITF_DESCR;
|
||||
typedef USB_ITF_DESCR __xdata *PXUSB_ITF_DESCR;
|
||||
|
||||
typedef struct _USB_ENDPOINT_DESCR {
|
||||
uint8_t bLength;
|
||||
@ -300,7 +257,7 @@ typedef struct _USB_ENDPOINT_DESCR {
|
||||
uint8_t bInterval;
|
||||
} USB_ENDP_DESCR, *PUSB_ENDP_DESCR;
|
||||
|
||||
typedef USB_ENDP_DESCR XDATA *PXUSB_ENDP_DESCR;
|
||||
typedef USB_ENDP_DESCR __xdata *PXUSB_ENDP_DESCR;
|
||||
|
||||
typedef struct _USB_CONFIG_DESCR_LONG {
|
||||
USB_CFG_DESCR cfg_descr;
|
||||
@ -308,7 +265,7 @@ typedef struct _USB_CONFIG_DESCR_LONG {
|
||||
USB_ENDP_DESCR endp_descr[1];
|
||||
} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG;
|
||||
|
||||
typedef USB_CFG_DESCR_LONG XDATA *PXUSB_CFG_DESCR_LONG;
|
||||
typedef USB_CFG_DESCR_LONG __xdata *PXUSB_CFG_DESCR_LONG;
|
||||
|
||||
typedef struct _USB_HUB_DESCR {
|
||||
uint8_t bDescLength;
|
||||
@ -322,7 +279,7 @@ typedef struct _USB_HUB_DESCR {
|
||||
uint8_t PortPwrCtrlMask;
|
||||
} USB_HUB_DESCR, *PUSB_HUB_DESCR;
|
||||
|
||||
typedef USB_HUB_DESCR XDATA *PXUSB_HUB_DESCR;
|
||||
typedef USB_HUB_DESCR __xdata *PXUSB_HUB_DESCR;
|
||||
|
||||
typedef struct _USB_HID_DESCR {
|
||||
uint8_t bLength;
|
||||
@ -336,9 +293,9 @@ typedef struct _USB_HID_DESCR {
|
||||
uint8_t wDescriptorLengthH;
|
||||
} USB_HID_DESCR, *PUSB_HID_DESCR;
|
||||
|
||||
typedef USB_HID_DESCR XDATA *PXUSB_HID_DESCR;
|
||||
typedef USB_HID_DESCR __xdata *PXUSB_HID_DESCR;
|
||||
|
||||
typedef struct _UDISK_BOC_CBW { /* Command of BulkOnly USB-FlashDisk */
|
||||
typedef struct _UDISK_BOC_CBW { /* command of BulkOnly USB-FlashDisk */
|
||||
uint8_t mCBW_Sig0;
|
||||
uint8_t mCBW_Sig1;
|
||||
uint8_t mCBW_Sig2;
|
||||
@ -350,16 +307,16 @@ typedef struct _UDISK_BOC_CBW { /* Command of BulkOnly USB-FlashDisk *
|
||||
uint8_t mCBW_DataLen0;
|
||||
uint8_t mCBW_DataLen1;
|
||||
uint8_t mCBW_DataLen2;
|
||||
uint8_t mCBW_DataLen3; /* MSB byte of data length, always is 0 */
|
||||
uint8_t mCBW_Flag; /* Transfer direction and etc. */
|
||||
uint8_t mCBW_DataLen3; /* uppest byte of data length, always is 0 */
|
||||
uint8_t mCBW_Flag; /* transfer direction and etc. */
|
||||
uint8_t mCBW_LUN;
|
||||
uint8_t mCBW_CB_Len; /* Length of command block */
|
||||
uint8_t mCBW_CB_Buf[16]; /* Command block buffer */
|
||||
uint8_t mCBW_CB_Len; /* length of command block */
|
||||
uint8_t mCBW_CB_Buf[16]; /* command block buffer */
|
||||
} UDISK_BOC_CBW, *PUDISK_BOC_CBW;
|
||||
|
||||
typedef UDISK_BOC_CBW XDATA *PXUDISK_BOC_CBW;
|
||||
typedef UDISK_BOC_CBW __xdata *PXUDISK_BOC_CBW;
|
||||
|
||||
typedef struct _UDISK_BOC_CSW { /* Status of BulkOnly USB-FlashDisk */
|
||||
typedef struct _UDISK_BOC_CSW { /* status of BulkOnly USB-FlashDisk */
|
||||
uint8_t mCSW_Sig0;
|
||||
uint8_t mCSW_Sig1;
|
||||
uint8_t mCSW_Sig2;
|
||||
@ -368,13 +325,13 @@ typedef struct _UDISK_BOC_CSW { /* Status of BulkOnly USB-FlashDisk */
|
||||
uint8_t mCSW_Tag1;
|
||||
uint8_t mCSW_Tag2;
|
||||
uint8_t mCSW_Tag3;
|
||||
uint8_t mCSW_Residue0; /* Return: remainder bytes */
|
||||
uint8_t mCSW_Residue0; /* return: remainder bytes */
|
||||
uint8_t mCSW_Residue1;
|
||||
uint8_t mCSW_Residue2;
|
||||
uint8_t mCSW_Residue3; /* MSB byte of remainder length, always is 0 */
|
||||
uint8_t mCSW_Status; /* Return: result status */
|
||||
uint8_t mCSW_Residue3; /* uppest byte of remainder length, always is 0 */
|
||||
uint8_t mCSW_Status; /* return: result status */
|
||||
} UDISK_BOC_CSW, *PUDISK_BOC_CSW;
|
||||
|
||||
typedef UDISK_BOC_CSW XDATA *PXUDISK_BOC_CSW;
|
||||
typedef UDISK_BOC_CSW __xdata *PXUDISK_BOC_CSW;
|
||||
|
||||
#endif // __USB_DEF__
|
||||
|
||||
@ -5,9 +5,9 @@
|
||||
* Date : 2017/01/20
|
||||
* Description : CH554 DEBUG Interface
|
||||
CH554 main frequency modification, delay function definition
|
||||
Serial port 0 and serial port 1 initialization
|
||||
Serial port 0 and serial port 1 transceiver subfunctions
|
||||
Watchdog initialization
|
||||
Serial port 0 and serial port 1 initialization
|
||||
Serial port 0 and serial port 1 transceiver subfunctions
|
||||
Watchdog initialization
|
||||
*******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
@ -18,8 +18,8 @@
|
||||
/*******************************************************************************
|
||||
* Function Name : CfgFsys( )
|
||||
* Description : CH554 clock selection and configuration function, Fsys 6MHz is used by default, FREQ_SYS can be passed
|
||||
CLOCK_CFG configuration, the formula is as follows:
|
||||
Fsys = (Fosc * 4 / (CLOCK_CFG & MASK_SYS_CK_SEL); the specific clock needs to be configured by yourself
|
||||
CLOCK_CFG configuration, the formula is as follows:
|
||||
Fsys = (Fosc * 4 / (CLOCK_CFG & MASK_SYS_CK_SEL); the specific clock needs to be configured by yourself
|
||||
*******************************************************************************/
|
||||
void CfgFsys( )
|
||||
{
|
||||
@ -51,6 +51,8 @@ void CfgFsys()
|
||||
SAFE_MOD = 0x00;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : mDelayus(UNIT16 n)
|
||||
* Description : us delay function
|
||||
@ -71,7 +73,7 @@ void mDelayuS(uint16_t n) // Delay in uS
|
||||
n >>= 4;
|
||||
#endif
|
||||
#endif
|
||||
while (n) { // Total = 12~13 Fsys cycles, 1uS @Fsys=12MHz
|
||||
while ( n ) { // total = 12~13 Fsys cycles, 1uS @Fsys=12MHz
|
||||
++ SAFE_MOD; // 2 Fsys cycles, for higher Fsys, add operation here
|
||||
#ifdef FREQ_SYS
|
||||
#if FREQ_SYS >= 14000000
|
||||
@ -137,8 +139,7 @@ void putchar(char c)
|
||||
SBUF = c;
|
||||
}
|
||||
|
||||
char getchar(void)
|
||||
{
|
||||
char getchar() {
|
||||
while(!RI); /* assumes UART is initialized */
|
||||
RI = 0;
|
||||
return SBUF;
|
||||
@ -153,8 +154,7 @@ int putchar(int c)
|
||||
return c;
|
||||
}
|
||||
|
||||
int getchar(void)
|
||||
{
|
||||
int getchar() {
|
||||
while(!RI); /* assumes UART is initialized */
|
||||
RI = 0;
|
||||
return SBUF;
|
||||
@ -162,8 +162,7 @@ int getchar(void)
|
||||
#endif
|
||||
|
||||
// Set pin p1.4 and p1.5 to GPIO output mode.
|
||||
void gpio_init()
|
||||
{
|
||||
void gpio_init(){
|
||||
// p1.4
|
||||
P1_MOD_OC &= ~0x10;
|
||||
P1_DIR_PU |= 0x10;
|
||||
@ -171,11 +170,12 @@ void gpio_init()
|
||||
// p1.5
|
||||
P1_MOD_OC &= ~0x20;
|
||||
P1_DIR_PU |= 0x20;
|
||||
|
||||
}
|
||||
|
||||
void gpio_set(uint8_t pin)
|
||||
void gpio_set(uint8_t pin) {
|
||||
switch (pin)
|
||||
{
|
||||
switch (pin) {
|
||||
case 0x10: // p1.4
|
||||
P1 |= 0x10;
|
||||
break;
|
||||
@ -187,9 +187,9 @@ void gpio_set(uint8_t pin)
|
||||
}
|
||||
}
|
||||
|
||||
void gpio_unset(uint8_t pin)
|
||||
void gpio_unset(uint8_t pin) {
|
||||
switch (pin)
|
||||
{
|
||||
switch (pin) {
|
||||
case 0x10:
|
||||
P1 &= ~0x10;
|
||||
break;
|
||||
@ -199,69 +199,5 @@ void gpio_unset(uint8_t pin)
|
||||
default: // do nothing, unsupported pin.
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t gpio_get(uint8_t pin)
|
||||
{
|
||||
uint8_t ret = 0;
|
||||
|
||||
switch (pin) {
|
||||
case 0x10: // p1.4
|
||||
ret = P1 & 0x10;
|
||||
break;
|
||||
case 0x20: // p1.5
|
||||
ret = P1 & 0x20;
|
||||
break;
|
||||
default: // do nothing, unsupported pin.
|
||||
ret = 0xff;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
// Set pin p1.4 to GPIO input mode. (FPGA_CTS)
|
||||
void gpio_init_p1_4_in()
|
||||
{
|
||||
// p1.4
|
||||
P1_MOD_OC &= ~0x10; // Output Mode: 0 = Push-pull output, 1 = Open-drain output
|
||||
P1_DIR_PU &= ~0x10; // Port Direction Control and Pull-up Enable Register:
|
||||
// Push-pull output mode:
|
||||
// 0 = Input.
|
||||
// 1 = Output
|
||||
// Open-drain output mode:
|
||||
// 0 = Pull-up resistor disabled
|
||||
// 1 = Pull-up resistor enabled
|
||||
}
|
||||
|
||||
// Read status of pin 1.4
|
||||
uint8_t gpio_p1_4_get(void)
|
||||
{
|
||||
return (P1 & 0x10); // p1.4
|
||||
}
|
||||
|
||||
// Set pin p1.5 to GPIO output mode. (CH552_CTS)
|
||||
void gpio_init_p1_5_out()
|
||||
{
|
||||
// p1.5
|
||||
P1_MOD_OC &= ~0x20; // Output Mode: 0 = Push-pull output, 1 = Open-drain output
|
||||
P1_DIR_PU |= 0x20; // Port Direction Control and Pull-up Enable Register:
|
||||
// Push-pull output mode:
|
||||
// 0 = Input.
|
||||
// 1 = Output
|
||||
// Open-drain output mode:
|
||||
// 0 = Pull-up resistor disabled
|
||||
// 1 = Pull-up resistor enabled
|
||||
}
|
||||
|
||||
// Set p1.5 high
|
||||
void gpio_p1_5_set(void)
|
||||
{
|
||||
P1 |= 0x20; // p1.4
|
||||
}
|
||||
|
||||
// Set p1.5 low
|
||||
void gpio_p1_5_unset(void)
|
||||
{
|
||||
P1 &= ~0x20;
|
||||
}
|
||||
|
||||
@ -1,105 +1,62 @@
|
||||
#ifndef __DEBUG_H__
|
||||
#define __DEBUG_H__
|
||||
|
||||
|
||||
/* Debug */
|
||||
/* Provide printf subroutine and delay function */
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "ch554.h"
|
||||
|
||||
// UART1 baud rates
|
||||
// Setting Actual % error
|
||||
//Std 9600 9615.38 0.16%
|
||||
// 14400 14492.75 0.64%
|
||||
//Std 19200 19230.77 0.16%
|
||||
//Std 38400 38461.54 0.16%
|
||||
//Std 57600 58823.53 2.12%
|
||||
// 100000 100000 0.00%
|
||||
//Std 115200 111111.1 -3.55%
|
||||
// 128000 142857.14 11.61%
|
||||
//Std 230400 250000 8.51%
|
||||
// 250000 250000 0%
|
||||
// 256000 333333.33 30.21%
|
||||
//Std 460800 500000 8.51%
|
||||
//Std 500000 500000 0%
|
||||
//Std 576000
|
||||
//Std 921600
|
||||
//Std 1000000 1000000 0.00%
|
||||
|
||||
#ifndef UART0_BAUD
|
||||
//#define UART0_BAUD 115200
|
||||
#define UART0_BAUD 1000000
|
||||
#define UART0_BAUD 9600
|
||||
#endif
|
||||
|
||||
#ifndef UART1_BAUD
|
||||
#define UART1_BAUD 500000
|
||||
//#define UART1_BAUD 1000000
|
||||
#define UART1_BAUD 9600
|
||||
#endif
|
||||
|
||||
void CfgFsys(void); // CH554 clock selection and configuration
|
||||
void CfgFsys( ); // CH554 clock selection and configuration
|
||||
|
||||
void mDelayuS (uint16_t n); // Delay in units of uS
|
||||
void mDelaymS (uint16_t n); // Delay in mS
|
||||
|
||||
// Set pin p1.4 and p1.5 to GPIO output mode.
|
||||
void gpio_init(void);
|
||||
void gpio_set(uint8_t pin);
|
||||
void gpio_unset(uint8_t pin);
|
||||
uint8_t gpio_get(uint8_t pin);
|
||||
|
||||
void gpio_init_p1_4_in(void);
|
||||
void gpio_init_p1_5_out(void);
|
||||
uint8_t gpio_p1_4_get(void);
|
||||
void gpio_p1_5_set(void);
|
||||
void gpio_p1_5_unset(void);
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : CH554UART0Alter()
|
||||
* Description : Set the alternate pin mappings for UART0 (RX on P1.2, TX on P1.3)
|
||||
* Description : CH554 serial port 0 pin mapping, serial port mapping to P0.2 and P0.3
|
||||
|
||||
*******************************************************************************/
|
||||
inline void CH554UART0Alter()
|
||||
{
|
||||
PIN_FUNC |= bUART0_PIN_X; // RX on P1.2, TX on P1.3
|
||||
PIN_FUNC |= bUART0_PIN_X; //串口映射到P1.2和P1.3
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : mInitSTDIO()
|
||||
* Description : CH554 UART0 is initialized
|
||||
* T1 is used as the baud rate generator of UART0 by default
|
||||
* T2 can also be used as baud rate generator
|
||||
* RX on P3.0, TX on P3.1
|
||||
* Description : CH554 serial port 0 is initialized, T1 is used as the baud rate generator of UART0 by default, T2 can also be used
|
||||
As a baud rate generator
|
||||
*******************************************************************************/
|
||||
inline void mInitSTDIO( )
|
||||
{
|
||||
uint32_t x;
|
||||
uint8_t x2;
|
||||
|
||||
SM0 = 0; // 8-bit data asynchronous communication
|
||||
SM1 = 1; // Variable baud rate, which is generated by timer T1 or T2
|
||||
|
||||
// With SM0=0 and SM1=1 we are now in UART0 Mode 1
|
||||
|
||||
SM2 = 0; // In Mode 1, SM2=0 gives that the Receive interrupt flag bit is set when receiving data and the reception is valid
|
||||
|
||||
SM0 = 0;
|
||||
SM1 = 1;
|
||||
SM2 = 0; //Serial port 0 usage mode 1
|
||||
//Use Timer1 as a baud rate generator
|
||||
RCLK = 0; //UART0 receive clock
|
||||
TCLK = 0; //UART0 transmit clock
|
||||
|
||||
PCON |= SMOD; // Set Fast mode for UART0 baud rate communication
|
||||
PCON |= SMOD;
|
||||
x = 10 * FREQ_SYS / UART0_BAUD / 16; //If you change the main frequency, be careful not to overflow the value of x
|
||||
x2 = x % 10;
|
||||
x /= 10;
|
||||
if (x2 >= 5) {
|
||||
x++; // Rounding
|
||||
}
|
||||
TMOD = (TMOD & ~bT1_GATE & ~bT1_CT & ~MASK_T1_MOD) | bT1_M1; // Timer1 as 8-bit auto-reload timer
|
||||
if ( x2 >= 5 ) x ++; //rounding
|
||||
|
||||
TMOD = TMOD & ~ bT1_GATE & ~ bT1_CT & ~ MASK_T1_MOD | bT1_M1; //0X20, Timer1 as 8-bit auto-reload timer
|
||||
T2MOD = T2MOD | bTMR_CLK | bT1_CLK; //Timer1 clock selection
|
||||
TH1 = 0-x; // 12MHz crystal oscillator, baud / 12 is the actual need to set the baud rate
|
||||
TH1 = 0-x; //12MHz crystal oscillator, buad / 12 is the actual need to set the baud rate
|
||||
TR1 = 1; //Start timer 1
|
||||
TI = 1; // Enable transmit interrupt
|
||||
REN = 1; // UART0 receive enable
|
||||
ES = 1; // UART0 interrupt enable
|
||||
TI = 1;
|
||||
REN = 1; //Serial 0 receive enable
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
@ -109,8 +66,7 @@ inline void mInitSTDIO( )
|
||||
*******************************************************************************/
|
||||
inline uint8_t CH554UART0RcvByte( )
|
||||
{
|
||||
while (RI == 0)
|
||||
; // Wait for uart rx interrupt flag
|
||||
while(RI == 0); // wait for uart rx interrupt flag
|
||||
RI = 0;
|
||||
return SBUF;
|
||||
}
|
||||
@ -122,100 +78,61 @@ inline uint8_t CH554UART0RcvByte()
|
||||
*******************************************************************************/
|
||||
inline void CH554UART0SendByte(uint8_t SendDat)
|
||||
{
|
||||
|
||||
SBUF = SendDat;
|
||||
while (TI == 0)
|
||||
; // Wait for transmit to finish (TI == 1)
|
||||
while(TI ==0); // wait for transmit to finish (TI == 1)
|
||||
TI = 0;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : CH554UART1Alter()
|
||||
* Description : Set the alternate pin mappings for UART1 (RX on P3.4, TX on P3.2)
|
||||
* Description : Set the alternate pin mappings for UART1 (TX on P3.2, RX on P3.4)
|
||||
*******************************************************************************/
|
||||
inline void CH554UART1Alter()
|
||||
{
|
||||
PIN_FUNC |= bUART1_PIN_X; // RX on P3.4, TX on P3.2
|
||||
PIN_FUNC |= bUART1_PIN_X;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UART1Setup()
|
||||
* Description : CH554 serial port 1 initialization
|
||||
* RX on P1.6, TX on P1.7
|
||||
*
|
||||
* Description : CH554串口1初始化
|
||||
*******************************************************************************/
|
||||
inline void UART1Setup()
|
||||
{
|
||||
U1SM0 = 0; // UART1 selects 8-bit data bit
|
||||
U1SMOD = 1; // Fast mode
|
||||
U1REN = 1; // Enable receiving
|
||||
// Should correct for rounding in SBAUD1 calculation
|
||||
SBAUD1 = 256 - FREQ_SYS/16/UART1_BAUD; // Calculation for Fast mode
|
||||
IE_UART1 = 1; // Enable UART1 interrupt
|
||||
IP_EX = bIP_UART1; // Serial port IRQ has high priority
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UART1Clean()
|
||||
* Description : Read out spurious data
|
||||
*******************************************************************************/
|
||||
inline void UART1Clean()
|
||||
{
|
||||
uint8_t tmp;
|
||||
|
||||
while (U1RI) {
|
||||
tmp = SBUF1;
|
||||
U1RI = 0;
|
||||
}
|
||||
U1SM0 = 0; //UART1选择8位数据位
|
||||
U1SMOD = 1; //快速模式
|
||||
U1REN = 1; //使能接收
|
||||
// should correct for rounding in SBAUD1 calculation
|
||||
SBAUD1 = 256 - FREQ_SYS/16/UART1_BAUD;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : CH554UART1RcvByte()
|
||||
* Description : CH554UART1 receives a byte
|
||||
* Description : CH554UART1接收一个字节
|
||||
* Return : SBUF
|
||||
*******************************************************************************/
|
||||
inline uint8_t CH554UART1RcvByte( )
|
||||
{
|
||||
while (U1RI == 0) // Query reception, interrupt mode is not required
|
||||
;
|
||||
while(U1RI == 0); //查询接收，中断方式可不用
|
||||
U1RI = 0;
|
||||
return SBUF1;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : CH554UART1SendByte(uint8_t SendDat)
|
||||
* Description : CH554UART1 sends a byte
|
||||
* Input : uint8_t SendDat; data to be sent
|
||||
* Description : CH554UART1发送一个字节
|
||||
* Input : uint8_t SendDat；要发送的数据
|
||||
*******************************************************************************/
|
||||
inline void CH554UART1SendByte(uint8_t SendDat)
|
||||
{
|
||||
SBUF1 = SendDat; // Query sending, the interrupt mode does not need the following two statements, but TI=0 is required before sending
|
||||
while (U1TI == 0)
|
||||
;
|
||||
SBUF1 = SendDat; //查询发送，中断方式可不用下面2条语句,但发送前需TI=0
|
||||
while(U1TI ==0);
|
||||
U1TI = 0;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : CH554UART1SendBuffer(uint8_t SendDat)
|
||||
* Description : CH554UART1 sends a complete buffer
|
||||
* Input : uint8_t *Buf; Data to be sent
|
||||
* Input : uint32_t Len; Length of data
|
||||
*******************************************************************************/
|
||||
inline void CH554UART1SendBuffer(uint8_t *Buf, uint32_t Len)
|
||||
{
|
||||
uint32_t Count = 0;
|
||||
while (Count < Len) {
|
||||
if (gpio_p1_4_get()) {
|
||||
SBUF1 = Buf[Count++];
|
||||
while (U1TI == 0)
|
||||
;
|
||||
U1TI = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#if SDCC < 370
|
||||
void putchar(char c);
|
||||
char getchar(void);
|
||||
char getchar();
|
||||
#else
|
||||
int putchar(int c);
|
||||
int getchar(void);
|
||||
@ -236,11 +153,12 @@ inline void CH554WDTModeSelect(uint8_t mode)
|
||||
SAFE_MOD = 0xaa; //Enter Safe Mode
|
||||
if(mode){
|
||||
GLOBAL_CFG |= bWDOG_EN; //Start watchdog reset
|
||||
} else {
|
||||
GLOBAL_CFG &= ~bWDOG_EN; //Start watchdog only as a timer
|
||||
}
|
||||
SAFE_MOD = 0x00; // Exit safe Mode
|
||||
|
||||
else GLOBAL_CFG &= ~bWDOG_EN; //Start watchdog only as a timer
|
||||
SAFE_MOD = 0x00; //exit safe Mode
|
||||
WDOG_COUNT = 0; //Watchdog assignment initial value
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
@ -255,7 +173,12 @@ inline void CH554WDTModeSelect(uint8_t mode)
|
||||
*******************************************************************************/
|
||||
inline void CH554WDTFeed(uint8_t tim)
|
||||
{
|
||||
|
||||
WDOG_COUNT = tim; // Watchdog counter assignment
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
// Set pin p1.4 and p1.5 to GPIO output mode.
|
||||
void gpio_init();
|
||||
void gpio_set(uint8_t pin);
|
||||
void gpio_unset(uint8_t pin);
|
||||
|
||||
@ -1,40 +0,0 @@
|
||||
#ifndef __MEM_PART_H__
|
||||
#define __MEM_PART_H__
|
||||
|
||||
// https://github.com/contiki-os/contiki/wiki/8051-Memory-Spaces
|
||||
|
||||
#ifdef BUILD_CODE
|
||||
#define IDATA __idata
|
||||
#define XDATA __xdata
|
||||
#define AT0000 __at(0x0000) // 0x000 0
|
||||
#define AT0008 __at(0x0008) // 0x008, 8
|
||||
#define AT0010 __at(0x0010) // 0x010, 16
|
||||
#define AT0040 __at(0x0040) // 0x040, 64
|
||||
#define AT0050 __at(0x0050) // 0x050, 80
|
||||
#define AT0080 __at(0x0080) // 0x080, 128
|
||||
#define AT0090 __at(0x0090) // 0x090, 144
|
||||
#define AT00C0 __at(0x00C0) // 0x0C0, 192
|
||||
#define AT00C8 __at(0x00C8) // 0x0C8, 200
|
||||
#define AT0110 __at(0x0110) // 0x110, 272
|
||||
#define AT0148 __at(0x0148) // 0x148, 328
|
||||
#define AT01C8 __at(0x01C8) // 0x1C8, 456
|
||||
#define FLASH __code
|
||||
#else
|
||||
#define IDATA
|
||||
#define XDATA
|
||||
#define AT0000
|
||||
#define AT0008
|
||||
#define AT0010
|
||||
#define AT0040
|
||||
#define AT0050
|
||||
#define AT0080
|
||||
#define AT0090
|
||||
#define AT00C0
|
||||
#define AT00C8
|
||||
#define AT0110
|
||||
#define AT0148
|
||||
#define AT01C8
|
||||
#define FLASH
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,188 +0,0 @@
|
||||
#include <stdint.h>
|
||||
|
||||
#include "debug.h"
|
||||
#include "print.h"
|
||||
|
||||
void printStr(uint8_t *str)
|
||||
{
|
||||
#ifdef DEBUG_PRINT
|
||||
while (*str != 0) {
|
||||
CH554UART0SendByte(*str);
|
||||
++str;
|
||||
}
|
||||
#else
|
||||
(void)str;
|
||||
#endif
|
||||
}
|
||||
|
||||
void printChar(uint8_t c)
|
||||
{
|
||||
#ifdef DEBUG_PRINT
|
||||
CH554UART0SendByte(c);
|
||||
#else
|
||||
(void)c;
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef USE_NUM_U8
|
||||
int8_t uint8_to_str(uint8_t *buf, uint8_t bufsize, uint8_t n)
|
||||
{
|
||||
uint8_t *start;
|
||||
|
||||
#ifdef USE_NEGATIVE_NUMS
|
||||
if (n < 0) { // Handle negative numbers.
|
||||
if (!bufsize) {
|
||||
return -1;
|
||||
}
|
||||
*buf++ = '-';
|
||||
bufsize--;
|
||||
}
|
||||
#endif
|
||||
|
||||
start = buf; // Remember the start of the string. This will come into play at the end.
|
||||
|
||||
do {
|
||||
// Handle the current digit.
|
||||
uint8_t digit;
|
||||
if (!bufsize) {
|
||||
return -1;
|
||||
}
|
||||
digit = n % 10;
|
||||
#ifdef USE_NEGATIVE_NUMS
|
||||
if (digit < 0) {
|
||||
digit *= -1;
|
||||
}
|
||||
#endif
|
||||
*buf++ = digit + '0';
|
||||
bufsize--;
|
||||
n /= 10;
|
||||
} while (n);
|
||||
|
||||
// Terminate the string.
|
||||
if (!bufsize) {
|
||||
return -1;
|
||||
}
|
||||
*buf = 0;
|
||||
|
||||
// We wrote the string backwards, i.e. with least significant digits first. Now reverse the string.
|
||||
--buf;
|
||||
while (start < buf) {
|
||||
uint8_t a = *start;
|
||||
*start = *buf;
|
||||
*buf = a;
|
||||
++start;
|
||||
--buf;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef USE_NUM_U32
|
||||
int8_t uint32_to_str(uint8_t *buf, uint8_t bufsize, uint32_t n)
|
||||
{
|
||||
uint8_t *start;
|
||||
|
||||
#ifdef USE_NEGATIVE_NUMS
|
||||
if (n < 0) { // Handle negative numbers.
|
||||
if (!bufsize) {
|
||||
return -1;
|
||||
}
|
||||
*buf++ = '-';
|
||||
bufsize--;
|
||||
}
|
||||
#endif
|
||||
|
||||
start = buf; // Remember the start of the string. This will come into play at the end.
|
||||
|
||||
do {
|
||||
// Handle the current digit.
|
||||
uint8_t digit;
|
||||
if (!bufsize) {
|
||||
return -1;
|
||||
}
|
||||
digit = n % 10;
|
||||
#ifdef USE_NEGATIVE_NUMS
|
||||
if (digit < 0) {
|
||||
digit *= -1;
|
||||
}
|
||||
#endif
|
||||
*buf++ = digit + '0';
|
||||
bufsize--;
|
||||
n /= 10;
|
||||
} while (n);
|
||||
|
||||
// Terminate the string.
|
||||
if (!bufsize) {
|
||||
return -1;
|
||||
}
|
||||
*buf = 0;
|
||||
|
||||
// We wrote the string backwards, i.e. with least significant digits first. Now reverse the string.
|
||||
--buf;
|
||||
while (start < buf) {
|
||||
uint8_t a = *start;
|
||||
*start = *buf;
|
||||
*buf = a;
|
||||
++start;
|
||||
--buf;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef USE_NUM_U8
|
||||
void printNumU8(uint8_t num)
|
||||
{
|
||||
#ifdef DEBUG_PRINT
|
||||
uint8_t num_str[4] = { 0 };
|
||||
int8_t ret;
|
||||
ret = uint8_to_str(num_str, 4, num);
|
||||
if (!ret) {
|
||||
printStr(num_str);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef USE_NUM_U32
|
||||
void printNumU32(uint32_t num)
|
||||
{
|
||||
#ifdef DEBUG_PRINT
|
||||
uint8_t num_str[11] = { 0 };
|
||||
int8_t ret;
|
||||
ret = uint32_to_str(num_str, 10, num);
|
||||
if (!ret) {
|
||||
printStr(num_str);
|
||||
}
|
||||
#else
|
||||
(void)num;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
void printNumHex(uint8_t num)
|
||||
{
|
||||
#ifdef DEBUG_PRINT
|
||||
// High nibble
|
||||
uint8_t val = num >> 4;
|
||||
if (val <= 9) {
|
||||
val = val + '0';
|
||||
} else {
|
||||
val = (val-10) + 'A';
|
||||
}
|
||||
printChar(val);
|
||||
|
||||
// Low nibble
|
||||
val = num & 0x0F;
|
||||
if (val <= 9) {
|
||||
val = val + '0';
|
||||
} else {
|
||||
val = (val-10) + 'A';
|
||||
}
|
||||
printChar(val);
|
||||
#else
|
||||
(void)num;
|
||||
#endif
|
||||
}
|
||||
@ -1,42 +0,0 @@
|
||||
#ifndef __PRINT_H__
|
||||
#define __PRINT_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
//#define DEBUG_PRINT
|
||||
//#define DEBUG_SETUP
|
||||
//#define UART_OUT_DEBUG
|
||||
//#define USE_NUM_U8
|
||||
#define USE_NUM_U32
|
||||
//#define USE_NEGATIVE_NUMS
|
||||
|
||||
void printStr(uint8_t *str);
|
||||
void printChar(uint8_t c);
|
||||
|
||||
#ifdef DEBUG_SETUP
|
||||
#define printStrSetup(x) printStr(x)
|
||||
#define printNumHexSetup(x) printNumHex(x)
|
||||
#else
|
||||
#define printStrSetup(x)
|
||||
#define printNumHexSetup(x)
|
||||
#endif
|
||||
|
||||
#ifdef USE_NUM_U8
|
||||
int8_t uint8_to_str(uint8_t *buf, uint8_t bufsize, uint8_t n);
|
||||
#endif
|
||||
|
||||
#ifdef USE_NUM_U32
|
||||
int8_t uint32_to_str(uint8_t *buf, uint8_t bufsize, uint32_t n);
|
||||
#endif
|
||||
|
||||
#ifdef USE_NUM_U8
|
||||
void printNumU8(uint8_t num);
|
||||
#endif
|
||||
|
||||
#ifdef USE_NUM_U32
|
||||
void printNumU32(uint32_t num);
|
||||
#endif
|
||||
|
||||
void printNumHex(uint8_t num);
|
||||
|
||||
#endif
|
||||
@ -1,64 +0,0 @@
|
||||
#ifndef __USB_STRINGS_H__
|
||||
#define __USB_STRINGS_H__
|
||||
|
||||
#include "mem.h"
|
||||
|
||||
unsigned char FLASH ProdDesc[]={ // "MTA1-USB-V1"
|
||||
24, // Length of this descriptor (in bytes)
|
||||
0x03, // Descriptor type (String)
|
||||
'M', 0, 'T', 0, 'A', 0, '1', 0,
|
||||
'-', 0, 'U', 0, 'S', 0, 'B', 0,
|
||||
'-', 0, 'V', 0, '1', 0
|
||||
};
|
||||
|
||||
unsigned char FLASH ManufDesc[]={ // "Tillitis"
|
||||
18, // Length of this descriptor (in bytes)
|
||||
0x03, // Descriptor type (String)
|
||||
'T', 0, 'i', 0, 'l', 0, 'l', 0,
|
||||
'i', 0, 't', 0, 'i', 0, 's', 0
|
||||
};
|
||||
|
||||
unsigned char FLASH SerialDesc[]={ // "68de5d27-e223-4874-bc76-a54d6e84068f"
|
||||
74, // Length of this descriptor (in bytes)
|
||||
0x03, // Descriptor type (String)
|
||||
'6', 0, '8', 0, 'd', 0, 'e', 0,
|
||||
'5', 0, 'd', 0, '2', 0, '7', 0,
|
||||
'-', 0, 'e', 0, '2', 0, '2', 0,
|
||||
'3', 0, '-', 0, '4', 0, '8', 0,
|
||||
'7', 0, '4', 0, '-', 0, 'b', 0,
|
||||
'c', 0, '7', 0, '6', 0, '-', 0,
|
||||
'a', 0, '5', 0, '4', 0, 'd', 0,
|
||||
'6', 0, 'e', 0, '8', 0, '4', 0,
|
||||
'0', 0, '6', 0, '8', 0, 'f', 0,
|
||||
};
|
||||
|
||||
unsigned char FLASH CdcCtrlInterfaceDesc[] = {
|
||||
18, // Length of this descriptor (in bytes)
|
||||
0x03, // Descriptor type (String)
|
||||
'C', 0, 'D', 0, 'C', 0, '-', 0,
|
||||
'C', 0, 't', 0, 'r', 0, 'l', 0,
|
||||
};
|
||||
|
||||
unsigned char FLASH CdcDataInterfaceDesc[] = {
|
||||
18, // Length of this descriptor (in bytes)
|
||||
0x03, // Descriptor type (String)
|
||||
'C', 0, 'D', 0, 'C', 0, '-', 0,
|
||||
'D', 0, 'a', 0, 't', 0, 'a', 0,
|
||||
};
|
||||
|
||||
unsigned char FLASH FidoHidInterfaceDesc[] = {
|
||||
18, // Length of this descriptor (in bytes)
|
||||
0x03, // Descriptor type (String)
|
||||
'F', 0, 'I', 0, 'D', 0, 'O', 0,
|
||||
'-', 0, 'H', 0, 'I', 0, 'D', 0,
|
||||
};
|
||||
|
||||
unsigned char FLASH TkeyCtrlInterfaceDesc[] = {
|
||||
20, // Length of this descriptor (in bytes)
|
||||
0x03, // Descriptor type (String)
|
||||
'T', 0, 'K', 0, 'E', 0, 'Y', 0,
|
||||
'-', 0, 'C', 0, 't', 0, 'r', 0,
|
||||
'l', 0,
|
||||
};
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
15
hw/usb_interface/ch552_fw/usb_strings.h
Normal file
15
hw/usb_interface/ch552_fw/usb_strings.h
Normal file
@ -0,0 +1,15 @@
|
||||
#ifndef USB_STRINGS
|
||||
#define USB_STRINGS
|
||||
unsigned char __code Prod_Des[]={ // "MTA1-USB-V1"
|
||||
0x18, 0x03, 0x4d, 0x00, 0x54, 0x00, 0x41, 0x00, 0x31, 0x00, 0x2d, 0x00, 0x55, 0x00, 0x53, 0x00, 0x42, 0x00, 0x2d, 0x00, 0x56, 0x00, 0x31, 0x00
|
||||
};
|
||||
|
||||
unsigned char __code Manuf_Des[]={ // "Tillitis"
|
||||
0x12, 0x03, 0x54, 0x00, 0x69, 0x00, 0x6c, 0x00, 0x6c, 0x00, 0x69, 0x00, 0x74, 0x00, 0x69, 0x00, 0x73, 0x00
|
||||
};
|
||||
|
||||
unsigned char __code SerDes[]={ // "68de5d27-e223-4874-bc76-a54d6e84068f"
|
||||
0x4a, 0x03, 0x36, 0x00, 0x38, 0x00, 0x64, 0x00, 0x65, 0x00, 0x35, 0x00, 0x64, 0x00, 0x32, 0x00, 0x37, 0x00, 0x2d, 0x00, 0x65, 0x00, 0x32, 0x00, 0x32, 0x00, 0x33, 0x00, 0x2d, 0x00, 0x34, 0x00, 0x38, 0x00, 0x37, 0x00, 0x34, 0x00, 0x2d, 0x00, 0x62, 0x00, 0x63, 0x00, 0x37, 0x00, 0x36, 0x00, 0x2d, 0x00, 0x61, 0x00, 0x35, 0x00, 0x34, 0x00, 0x64, 0x00, 0x36, 0x00, 0x65, 0x00, 0x38, 0x00, 0x34, 0x00, 0x30, 0x00, 0x36, 0x00, 0x38, 0x00, 0x66, 0x00
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
x
Reference in New Issue
Block a user