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(fpga) Possibly working syscall hw functionality.

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We don't want to set which address the CPU should jump to when
       a syscall is made, we want to push the jump instruction to
       execute. If that works.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2024-08-29 15:02:04 +02:00
parent e8762d80fc
commit fe8350422f
No known key found for this signature in database
GPG Key ID: 865B8A548EA61679
2 changed files with 31 additions and 26 deletions
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33
hw/application_fpga/core/tk1/rtl/tk1.v
View File

@ -26,7 +26,7 @@ module tk1(
output wire force_trap, output wire force_trap,
output system_reset, output system_reset,
output wire [31 : 0] syscall_addr, output wire [31 : 0] syscall_instr,
output wire syscall, output wire syscall,
output wire [14 : 0] ram_addr_rand, output wire [14 : 0] ram_addr_rand,
@ -84,7 +84,7 @@ module tk1(
localparam ADDR_BLAKE2S = 8'h10; localparam ADDR_BLAKE2S = 8'h10;
localparam ADDR_SYSCALL_ADDR = 8'h12; localparam ADDR_SYSCALL_INSTR = 8'h12;
localparam ADDR_SYSCALL_START = 8'h13; localparam ADDR_SYSCALL_START = 8'h13;
localparam ADDR_CDI_FIRST = 8'h20; localparam ADDR_CDI_FIRST = 8'h20;
@ -144,8 +144,11 @@ module tk1(
reg [31 : 0] blake2s_addr_reg; reg [31 : 0] blake2s_addr_reg;
reg blake2s_addr_we; reg blake2s_addr_we;
reg [31 : 0] syscall_addr_reg; reg [31 : 0] syscall_instr_reg;
reg syscall_addr_we; reg syscall_instr_we;
reg syscall_reg;
reg syscall_new;
reg [23 : 0] cpu_trap_ctr_reg; reg [23 : 0] cpu_trap_ctr_reg;
reg [23 : 0] cpu_trap_ctr_new; reg [23 : 0] cpu_trap_ctr_new;
@ -215,8 +218,8 @@ module tk1(
assign system_reset = system_reset_reg; assign system_reset = system_reset_reg;
assign syscall_addr = syscall_addr_reg; assign syscall_instr = syscall_instr_reg;
assign syscall = start_syscall; assign syscall = syscall_reg;
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -282,7 +285,8 @@ module tk1(
app_start_reg <= 32'h0; app_start_reg <= 32'h0;
app_size_reg <= 32'h0; app_size_reg <= 32'h0;
blake2s_addr_reg <= 32'h0; blake2s_addr_reg <= 32'h0;
syscall_addr_reg <= 32'h0; syscall_instr_reg <= 32'h0;
syscall_reg <= 1'h0;
cdi_mem[0] <= 32'h0; cdi_mem[0] <= 32'h0;
cdi_mem[1] <= 32'h0; cdi_mem[1] <= 32'h0;
cdi_mem[2] <= 32'h0; cdi_mem[2] <= 32'h0;
@ -306,6 +310,7 @@ module tk1(
cpu_trap_ctr_reg <= cpu_trap_ctr_new; cpu_trap_ctr_reg <= cpu_trap_ctr_new;
system_reset_reg <= system_reset_new; system_reset_reg <= system_reset_new;
syscall_reg <= syscall_new;
gpio1_reg[0] <= gpio1; gpio1_reg[0] <= gpio1;
gpio1_reg[1] <= gpio1_reg[0]; gpio1_reg[1] <= gpio1_reg[0];
@ -341,8 +346,8 @@ module tk1(
blake2s_addr_reg <= write_data; blake2s_addr_reg <= write_data;
end end
if (syscall_addr_we) begin if (syscall_instr_we) begin
syscall_addr_reg <= write_data; syscall_instr_reg <= write_data;
end end
if (cdi_mem_we) begin if (cdi_mem_we) begin
@ -455,8 +460,8 @@ module tk1(
app_start_we = 1'h0; app_start_we = 1'h0;
app_size_we = 1'h0; app_size_we = 1'h0;
blake2s_addr_we = 1'h0; blake2s_addr_we = 1'h0;
syscall_addr_we = 1'h0; syscall_instr_we = 1'h0;
start_syscall = 1'h0; syscall_new = 1'h0;
cdi_mem_we = 1'h0; cdi_mem_we = 1'h0;
cdi_mem_we = 1'h0; cdi_mem_we = 1'h0;
ram_addr_rand_we = 1'h0; ram_addr_rand_we = 1'h0;
@ -516,14 +521,14 @@ module tk1(
end end
end end
if (address == ADDR_SYSCALL_ADDR) begin if (address == ADDR_SYSCALL_INSTR) begin
if (!switch_app_reg) begin if (!switch_app_reg) begin
syscall_addr_we = 1'h1; syscall_instr_we = 1'h1;
end end
end end
if (address == ADDR_SYSCALL_START) begin if (address == ADDR_SYSCALL_START) begin
start_syscall = 1'h1; syscall_new = 1'h1;
end end
if ((address >= ADDR_CDI_FIRST) && (address <= ADDR_CDI_LAST)) begin if ((address >= ADDR_CDI_FIRST) && (address <= ADDR_CDI_LAST)) begin

24
hw/application_fpga/rtl/application_fpga.v
View File

@ -149,7 +149,7 @@ module application_fpga(
wire [14 : 0] ram_addr_rand; wire [14 : 0] ram_addr_rand;
wire [31 : 0] ram_data_rand; wire [31 : 0] ram_data_rand;
wire tk1_system_reset; wire tk1_system_reset;
wire [31 : 0] tk1_syscall_addr; wire [31 : 0] tk1_syscall_instr;
wire tk1_syscall; wire tk1_syscall;
/* verilator lint_on UNOPTFLAT */ /* verilator lint_on UNOPTFLAT */
@ -330,7 +330,7 @@ module application_fpga(
.system_reset(tk1_system_reset), .system_reset(tk1_system_reset),
.syscall_addr(tk1_syscall_addr), .syscall_instr(tk1_syscall_instr),
.syscall(tk1_syscall), .syscall(tk1_syscall),
.ram_addr_rand(ram_addr_rand), .ram_addr_rand(ram_addr_rand),
@ -439,6 +439,12 @@ module application_fpga(
muxed_rdata_new = ILLEGAL_INSTRUCTION; muxed_rdata_new = ILLEGAL_INSTRUCTION;
muxed_ready_new = 1'h1; muxed_ready_new = 1'h1;
end end
else if (tk1_syscall) begin
muxed_rdata_new = tk1_syscall_instr;
muxed_ready_new = 1'h1;
end
else begin else begin
case (area_prefix) case (area_prefix)
ROM_PREFIX: begin ROM_PREFIX: begin
@ -448,16 +454,10 @@ module application_fpga(
end end
RAM_PREFIX: begin RAM_PREFIX: begin
if (tk1_syscall) begin ram_cs = 1'h1;
muxed_rdata_new = tk1_syscall_addr; ram_we = cpu_wstrb;
muxed_ready_new = 1'h1; muxed_rdata_new = ram_read_data ^ ram_data_rand ^ {2{cpu_addr[15 : 0]}};
end muxed_ready_new = ram_ready;
else begin
ram_cs = 1'h1;
ram_we = cpu_wstrb;
muxed_rdata_new = ram_read_data ^ ram_data_rand ^ {2{cpu_addr[15 : 0]}};
muxed_ready_new = ram_ready;
end
end end
RESERVED_PREFIX: begin RESERVED_PREFIX: begin