Adding testbench and simulation targets for the SPI master.
This commit is contained in:
Joachim Strömbergson
dehanj
parent
59b6f897fb
commit
fdea1bdfcd
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@ -62,3 +62,4 @@ fp-info-cache
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*.ses
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__pycache__
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MEM.TXT
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@ -249,4 +249,17 @@ https://www.mouser.se/datasheet/2/949/w25q80dv_dl_revh_10022015-1489677.pdf
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The core is implemented as a single module. Future versions will
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probably be separated into separate modules.
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## Winbond Flash memory model
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The testbench for the SPI master requires a memory model of the
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Winbond Flash memory. The model [can be downloaded from
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Winbond](https://www.winbond.com/hq/support/documentation/downloadV2022.jsp?__locale=en&xmlPath=/support/resources/.content/item/DA02-KAG049.html&level=2)
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by providing the requested information and supplying the received
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verification code.
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From the downloaded file 'W25Q80DL.zip', please extract the file
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W25Q80DL.v and place it in the 'tb' directory before building the
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simulation model.
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---
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@ -58,6 +58,10 @@ module tb_tk1();
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localparam ADDR_CPU_MON_FIRST = 8'h61;
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localparam ADDR_CPU_MON_LAST = 8'h62;
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localparam ADDR_SPI_EN = 8'h80;
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localparam ADDR_SPI_XFER = 8'h81;
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localparam ADDR_SPI_DATA = 8'h82;
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//----------------------------------------------------------------
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// Register and Wire declarations.
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@ -89,6 +93,11 @@ module tb_tk1();
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wire tb_gpio3;
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wire tb_gpio4;
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wire tb_spi_ss;
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wire tb_spi_sck;
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wire tb_spi_mosi;
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wire tb_spi_miso;
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reg tb_cs;
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reg tb_we;
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reg [7 : 0] tb_address;
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@ -96,6 +105,12 @@ module tb_tk1();
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wire [31 : 0] tb_read_data;
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wire tb_ready;
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//----------------------------------------------------------------
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// Continuous assignments.
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//----------------------------------------------------------------
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// Inverted loopback of SPI data lines.
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assign tb_spi_miso = ~tb_spi_mosi;
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//----------------------------------------------------------------
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// Device Under Test.
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@ -124,6 +139,11 @@ module tb_tk1();
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.gpio3(tb_gpio3),
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.gpio4(tb_gpio4),
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.spi_ss(tb_spi_ss),
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.spi_sck(tb_spi_sck),
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.spi_mosi(tb_spi_mosi),
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.spi_miso(tb_spi_miso),
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.cs(tb_cs),
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.we(tb_we),
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.address(tb_address),
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@ -614,7 +634,38 @@ module tb_tk1();
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$display("--- test9: completed.");
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$display("");
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end
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endtask // test8
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endtask // test9
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//----------------------------------------------------------------
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// test10()
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// SPI master loopback test.
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//----------------------------------------------------------------
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task test10;
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begin
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tc_ctr = tc_ctr + 1;
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$display("");
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$display("--- test10: Loopback in SPI Master started.");
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$display("--- test10: Sending a byte.");
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write_word(ADDR_SPI_EN, 32'h1);
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write_word(ADDR_SPI_DATA, 32'ha7);
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write_word(ADDR_SPI_XFER, 32'h1);
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while (!dut.spi_ready) begin
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#(CLK_PERIOD);
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end
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$display("--- test10: Byte should have been sent.");
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write_word(ADDR_SPI_EN, 32'h0);
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// 0x58 is the inverse of 0xa7.
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read_word(ADDR_SPI_DATA, 32'h58);
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$display("--- test10: completed.");
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$display("");
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end
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endtask // test10
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//----------------------------------------------------------------
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@ -639,6 +690,8 @@ module tb_tk1();
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test7();
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test8();
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test9();
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test9();
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test10();
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display_test_result();
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$display("");
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@ -0,0 +1,732 @@
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//======================================================================
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//
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// tb_tk1_spi_master.v
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// -------------------
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// Testbench for the TK1_SPI_MASTER core.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2023 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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`timescale 1ns / 1ns
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module tb_tk1_spi_master();
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//----------------------------------------------------------------
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// Internal constant and parameter definitions.
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//----------------------------------------------------------------
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parameter DEBUG = 1;
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parameter CLK_HALF_PERIOD = 1;
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parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
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parameter MISO_ALL_ZERO = 0;
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parameter MISO_ALL_ONE = 1;
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parameter MISO_MOSI = 2;
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parameter MISO_INV_MOSI = 3;
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//----------------------------------------------------------------
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// Register and Wire declarations.
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//----------------------------------------------------------------
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reg [31 : 0] cycle_ctr;
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reg [31 : 0] error_ctr;
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reg [31 : 0] tc_ctr;
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reg monitor;
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reg verbose;
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reg tb_clk;
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reg tb_reset_n;
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wire tb_spi_ss;
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wire tb_spi_sck;
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wire tb_spi_mosi;
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wire tb_spi_miso;
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reg tb_spi_enable;
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reg tb_spi_enable_vld;
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reg tb_spi_start;
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reg [7 : 0] tb_spi_tx_data;
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reg tb_spi_tx_data_vld;
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wire [7 : 0] tb_spi_rx_data;
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wire tb_spi_ready;
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wire mem_model_WPn;
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wire mem_model_HOLDn;
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reg [1 : 0] tb_miso_mux_ctrl;
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reg my_tb_spi_ss;
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//----------------------------------------------------------------
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// Assignments.
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//----------------------------------------------------------------
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assign mem_model_WPn = 1'h1;
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//----------------------------------------------------------------
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// Device Under Test.
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//----------------------------------------------------------------
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tk1_spi_master dut(
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.clk(tb_clk),
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.reset_n(tb_reset_n),
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.spi_ss(tb_spi_ss),
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.spi_sck(tb_spi_sck),
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.spi_mosi(tb_spi_mosi),
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.spi_miso(tb_spi_miso),
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.spi_enable(tb_spi_enable),
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.spi_enable_vld(tb_spi_enable_vld),
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.spi_start(tb_spi_start),
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.spi_tx_data(tb_spi_tx_data),
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.spi_tx_data_vld(tb_spi_tx_data_vld),
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.spi_rx_data(tb_spi_rx_data),
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.spi_ready(tb_spi_ready)
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);
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//----------------------------------------------------------------
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// spi_memory
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//----------------------------------------------------------------
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W25Q80DL spi_memory(
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.CSn(tb_spi_ss),
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.CLK(tb_spi_sck),
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.DIO(tb_spi_mosi),
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.DO(tb_spi_miso),
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.WPn(mem_model_WPn),
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.HOLDn(mem_model_HOLDn)
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);
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//----------------------------------------------------------------
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// clk_gen
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//
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// Always running clock generator process.
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//----------------------------------------------------------------
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always
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begin : clk_gen
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#CLK_HALF_PERIOD;
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tb_clk = !tb_clk;
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end // clk_gen
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//----------------------------------------------------------------
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// sys_monitor()
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//
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// An always running process that creates a cycle counter and
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// conditionally displays information about the DUT.
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//----------------------------------------------------------------
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always
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begin : sys_monitor
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cycle_ctr = cycle_ctr + 1;
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#(CLK_PERIOD);
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if (monitor)
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begin
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dump_dut_state();
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end
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end
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//----------------------------------------------------------------
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// dump_dut_state()
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//
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// Dump the state of the dump when needed.
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//----------------------------------------------------------------
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task dump_dut_state;
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begin : dump_dut_state
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$display("");
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$display("State of DUT at cycle: %08d", cycle_ctr);
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$display("------------");
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$display("Inputs and outputs:");
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$display("spi_ss: 0x%1x, spi_sck: 0x%1x, spi_mosi: 0x%1x, spi_miso:0x%1x",
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dut.spi_ss, dut.spi_sck, dut.spi_mosi, dut.spi_miso);
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$display("spi_enable_vld: 0x%1x, spi_enable: 0x%1x",
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dut.spi_enable_vld, dut.spi_enable);
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$display("spi_tx_data_vld: 0x%1x, spi_tx_data: 0x%02x",
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dut.spi_tx_data_vld, dut.spi_tx_data);
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$display("spi_start: 0x%1x, spi_ready: 0x%1x, spi_rx_data: 0x%02x",
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dut.spi_start, dut.spi_ready, dut.spi_rx_data);
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$display("");
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$display("");
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$display("Internal state:");
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$display("spi_clk_ctr_rst: 0x%1x, spi_clk_ctr_reg: 0x%02x",
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dut.spi_clk_ctr_rst, dut.spi_clk_ctr_reg);
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$display("");
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$display("spi_bit_ctr_rst: 0x%1x, spi_bit_ctr_inc: 0x%1x, spi_bit_ctr_reg: 0x%02x",
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dut.spi_bit_ctr_rst, dut.spi_bit_ctr_inc, dut.spi_bit_ctr_reg);
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$display("");
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$display("spi_ctrl_reg: 0x%02x, spi_ctrl_new: 0x%02x, spi_ctrl_we: 0x%1x",
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dut.spi_ctrl_reg, dut.spi_ctrl_new, dut.spi_ctrl_we);
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$display("");
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$display("spi_tx_data_new: 0x%1x, spi_tx_data_nxt: 0x%1x, spi_tx_data_we: 0x%1x",
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dut.spi_tx_data_new, dut.spi_tx_data_nxt, dut.spi_tx_data_we);
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$display("spi_tx_data_reg: 0x%02x, spi_tx_data_new: 0x%02x",
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dut.spi_tx_data_reg, dut.spi_tx_data_new);
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$display("");
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$display("spi_rx_data_nxt: 0x%1x, spi_rx_data_we: 0x%1x",
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dut.spi_rx_data_nxt, dut.spi_rx_data_we);
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$display("spi_rx_data_reg: 0x%02x, spi_rx_data_new: 0x%02x",
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dut.spi_rx_data_reg, dut.spi_rx_data_new);
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$display("spi_rx_data_reg0: 0x%1x, spi_rx_data_new0: 0x%1x",
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dut.spi_rx_data_reg[0], dut.spi_rx_data_new[0]);
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$display("spi_rx_data_reg1: 0x%1x, spi_rx_data_new1: 0x%1x",
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dut.spi_rx_data_reg[1], dut.spi_rx_data_new[1]);
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$display("spi_rx_data_reg2: 0x%1x, spi_rx_data_new2: 0x%1x",
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dut.spi_rx_data_reg[2], dut.spi_rx_data_new[2]);
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$display("spi_rx_data_reg3: 0x%1x, spi_rx_data_new3: 0x%1x",
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dut.spi_rx_data_reg[3], dut.spi_rx_data_new[3]);
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$display("spi_rx_data_reg4: 0x%1x, spi_rx_data_new4: 0x%1x",
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dut.spi_rx_data_reg[4], dut.spi_rx_data_new[4]);
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$display("spi_rx_data_reg5: 0x%1x, spi_rx_data_new5: 0x%1x",
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dut.spi_rx_data_reg[5], dut.spi_rx_data_new[5]);
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$display("spi_rx_data_reg6: 0x%1x, spi_rx_data_new6: 0x%1x",
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dut.spi_rx_data_reg[6], dut.spi_rx_data_new[6]);
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$display("spi_rx_data_reg7: 0x%1x, spi_rx_data_new7: 0x%1x",
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dut.spi_rx_data_reg[7], dut.spi_rx_data_new[7]);
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$display("");
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end
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endtask // dump_dut_state
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//----------------------------------------------------------------
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// reset_dut()
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//
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// Toggle reset to put the DUT into a well known state.
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//----------------------------------------------------------------
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task reset_dut;
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begin
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$display("--- Toggle reset.");
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tb_reset_n = 0;
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#(2 * CLK_PERIOD);
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tb_reset_n = 1;
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end
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endtask // reset_dut
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//----------------------------------------------------------------
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// display_test_result()
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//
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// Display the accumulated test results.
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//----------------------------------------------------------------
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task display_test_result;
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begin
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if (error_ctr == 0)
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begin
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$display("--- All %02d test cases completed successfully", tc_ctr);
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end
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else
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begin
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$display("--- %02d tests completed - %02d test cases did not complete successfully.",
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tc_ctr, error_ctr);
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end
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end
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endtask // display_test_result
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//----------------------------------------------------------------
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// init_sim()
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//
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// Initialize all counters and testbed functionality as well
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// as setting the DUT inputs to defined values.
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//----------------------------------------------------------------
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task init_sim;
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begin
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cycle_ctr = 0;
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error_ctr = 0;
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tc_ctr = 0;
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monitor = 0;
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tb_clk = 1'h0;
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tb_reset_n = 1'h1;
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tb_spi_enable = 1'h0;
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tb_spi_enable_vld = 1'h0;
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tb_spi_start = 1'h0;
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tb_spi_tx_data = 8'h0;
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tb_spi_tx_data_vld = 1'h0;
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tb_miso_mux_ctrl = MISO_MOSI;
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end
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endtask // init_sim
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//----------------------------------------------------------------
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// enable_spi
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//
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// Enable the SPI-interface
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//----------------------------------------------------------------
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task enable_spi;
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begin
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if (verbose) begin
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$display("enable_spi: Started");
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end
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tb_spi_enable = 1'h1;
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tb_spi_enable_vld = 1'h1;
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#(CLK_PERIOD);
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tb_spi_enable_vld = 1'h0;
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#(CLK_PERIOD);
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if (verbose) begin
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$display("enable_spi: Completed");
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end
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end
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endtask // enable_spi
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//----------------------------------------------------------------
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// disable_spi
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//
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// Disable the SPI-interface
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//----------------------------------------------------------------
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task disable_spi;
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begin
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if (verbose) begin
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$display("disable_spi: Started");
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end
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tb_spi_enable = 1'h0;
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tb_spi_enable_vld = 1'h1;
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#(CLK_PERIOD);
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tb_spi_enable_vld = 1'h0;
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#(CLK_PERIOD);
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if (verbose) begin
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$display("disable_spi: Completed");
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end
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end
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endtask // disable_spi
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//----------------------------------------------------------------
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// xfer_byte
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//
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// Wait until the SPI-master is ready, then send input byte
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// and return the received byte.
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//----------------------------------------------------------------
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task xfer_byte (input [7 : 0] to_mem, output [7 : 0] from_mem);
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begin
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if (verbose) begin
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$display("xfer_byte: Trying to send 0x%02x to mem", to_mem);
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end
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tb_spi_tx_data = to_mem;
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tb_spi_tx_data_vld = 1'h1;
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#(CLK_PERIOD);
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tb_spi_tx_data_vld = 1'h0;
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#(CLK_PERIOD);
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while (tb_spi_ready == 1'h0) begin
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#(CLK_PERIOD);
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end
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#(CLK_PERIOD);
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tb_spi_start = 1'h1;
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#(CLK_PERIOD);
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tb_spi_start = 1'h0;
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#(CLK_PERIOD);
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while (tb_spi_ready == 1'h0) begin
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#(CLK_PERIOD);
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end
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#(CLK_PERIOD);
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from_mem = tb_spi_rx_data;
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#(CLK_PERIOD);
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if (verbose) begin
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$display("xfer_byte: Received 0x%02x from mem", from_mem);
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end
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end
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endtask // xfer_byte
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//----------------------------------------------------------------
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// read_mem_range()
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//
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// Read out a specified memory range. Result is printed,
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//----------------------------------------------------------------
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task read_mem_range (input [23 : 0] address, input integer num_bytes);
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begin : read_mem_range
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reg [7 : 0] rx_byte;
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integer i;
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if (verbose) begin
|
||||
$display("read_mem_range: Reading out %d bytes starting at address 0x%06x", num_bytes, address);
|
||||
end
|
||||
|
||||
#(2 * CLK_PERIOD);
|
||||
enable_spi();
|
||||
#(2 * CLK_PERIOD);
|
||||
|
||||
// Send read command 0x03.
|
||||
xfer_byte(8'h03, rx_byte);
|
||||
|
||||
// Send adress 0x000000.
|
||||
xfer_byte(address[23 : 16], rx_byte);
|
||||
xfer_byte(address[15 : 8], rx_byte);
|
||||
xfer_byte(address[7 : 0], rx_byte);
|
||||
|
||||
// Read out num_bytes bytes.
|
||||
for (i = 0 ; i < num_bytes ; i = i + 1) begin
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
$display("--- tc_read_mem_range: Byte 0x%06x: 0x%02x", address + i, rx_byte);
|
||||
end
|
||||
|
||||
disable_spi();
|
||||
#(2 * CLK_PERIOD);
|
||||
|
||||
if (verbose) begin
|
||||
$display("read_mem_range: Completed");
|
||||
end
|
||||
end
|
||||
endtask // read_mem_range
|
||||
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// read_status()
|
||||
//----------------------------------------------------------------
|
||||
task read_status ();
|
||||
begin : read_status
|
||||
reg [7 : 0] dummy;
|
||||
reg [15 : 0] status;
|
||||
enable_spi();
|
||||
#(2 * CLK_PERIOD);
|
||||
xfer_byte(8'h05, dummy);
|
||||
xfer_byte(8'h00, status[15 : 8]);
|
||||
xfer_byte(8'h00, status[7 : 0]);
|
||||
#(2 * CLK_PERIOD);
|
||||
disable_spi();
|
||||
$display("--- read_status: 0x%04x", status);
|
||||
end
|
||||
endtask // read_status
|
||||
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// tc_get_device_id()
|
||||
//
|
||||
// Test case that reads out the device ID.
|
||||
//----------------------------------------------------------------
|
||||
task tc_get_device_id;
|
||||
begin : tc_get_id
|
||||
reg [7 : 0] rx_byte;
|
||||
tc_ctr = tc_ctr + 1;
|
||||
monitor = 0;
|
||||
|
||||
$display("");
|
||||
$display("--- tc_get_device_id: Read out device id from the memory.");
|
||||
|
||||
#(2 * CLK_PERIOD);
|
||||
enable_spi();
|
||||
#(2 * CLK_PERIOD);
|
||||
|
||||
// Send 0xab command.
|
||||
$display("--- tc_get_device_id: Sending 0xab command.");
|
||||
xfer_byte(8'hab, rx_byte);
|
||||
#(CLK_PERIOD);
|
||||
|
||||
// Dummy bytes.
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
$display("--- tc_get_device_id: Got 0x%02x after dummy byte 1", rx_byte);
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
$display("--- tc_get_device_id: Got 0x%02x after dummy byte 2", rx_byte);
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
$display("--- tc_get_device_id: Got 0x%02x after dummy byte 3", rx_byte);
|
||||
|
||||
// Get the ID byte.
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
$display("--- tc_get_device_id: Got ID 0x%02x after dummy byte 4", rx_byte);
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
$display("--- tc_get_device_id: Got ID 0x%02x after dummy byte 5", rx_byte);
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
$display("--- tc_get_device_id: Got ID 0x%02x after dummy byte 6", rx_byte);
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
$display("--- tc_get_device_id: Got ID 0x%02x after dummy byte 6", rx_byte);
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
$display("--- tc_get_device_id: Got ID 0x%02x after dummy byte 6", rx_byte);
|
||||
|
||||
disable_spi();
|
||||
#(2 * CLK_PERIOD);
|
||||
|
||||
$display("--- tc_get_device_id: completed.");
|
||||
$display("");
|
||||
end
|
||||
endtask // tc_get_device_id
|
||||
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// tc_get_jedec_id()
|
||||
//
|
||||
// Test case that reads out the JEDEC ID.
|
||||
//----------------------------------------------------------------
|
||||
task tc_get_jedec_id;
|
||||
begin : tc_get_id
|
||||
reg [7 : 0] rx_byte;
|
||||
tc_ctr = tc_ctr + 1;
|
||||
monitor = 0;
|
||||
verbose = 0;
|
||||
|
||||
$display("");
|
||||
$display("--- tc_get_jedec_id: Read out JEDEC device id, type and capacity from the memory.");
|
||||
|
||||
#(2 * CLK_PERIOD);
|
||||
enable_spi();
|
||||
#(2 * CLK_PERIOD);
|
||||
|
||||
// Send 0x9f command.
|
||||
$display("--- tc_get_jedec_id: Sending 0xab command.");
|
||||
xfer_byte(8'h9f, rx_byte);
|
||||
|
||||
// Send dummy bytes and get response back.
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
$display("--- tc_get_jedec_id: Got manufacture ID 0x%02x", rx_byte);
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
$display("--- tc_get_jedec_id: Got memory type 0x%02x", rx_byte);
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
$display("--- tc_get_jedec_id: Got memory capacity 0x%02x", rx_byte);
|
||||
|
||||
disable_spi();
|
||||
#(2 * CLK_PERIOD);
|
||||
|
||||
$display("--- tc_get_jedec_id: completed.");
|
||||
$display("");
|
||||
|
||||
verbose = 1;
|
||||
end
|
||||
endtask // tc_get_jedec_id
|
||||
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// tc_get_unique_device_id()
|
||||
//
|
||||
// Test case that reads out the JEDEC ID.
|
||||
// Expected: 0xdc02030405060708
|
||||
//----------------------------------------------------------------
|
||||
task tc_get_unique_device_id;
|
||||
begin : tc_get_id
|
||||
reg [7 : 0] rx_byte;
|
||||
integer i;
|
||||
tc_ctr = tc_ctr + 1;
|
||||
monitor = 0;
|
||||
verbose = 0;
|
||||
|
||||
$display("");
|
||||
$display("--- tc_get_unique_device_id: Read out unique id from the memory");
|
||||
$display("--- tc_get_unique_device_id: Expected result: 0xdc02030405060708");
|
||||
|
||||
#(2 * CLK_PERIOD);
|
||||
enable_spi();
|
||||
#(2 * CLK_PERIOD);
|
||||
|
||||
// Send 0x9f command.
|
||||
$display("--- tc_get_unique_device_id: Sending 0x4b command.");
|
||||
xfer_byte(8'h4b, rx_byte);
|
||||
|
||||
// Send four dummy bytes and get response back.
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
|
||||
// Send eight bytes and get unique device id back.
|
||||
$display("--- tc_get_unique_device_id: reading out the unique device UD");
|
||||
for (i = 0 ; i < 8 ; i = i + 1) begin
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
$display("--- tc_get_unique_device_id: 0x%02x", rx_byte);
|
||||
end
|
||||
|
||||
disable_spi();
|
||||
#(2 * CLK_PERIOD);
|
||||
|
||||
$display("--- tc_get_unique_device_id: completed.");
|
||||
$display("");
|
||||
|
||||
verbose = 1;
|
||||
end
|
||||
endtask // tc_get_unique_device_id
|
||||
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// tc_get_manufacturer_id()
|
||||
//
|
||||
// Test case that reads out the device ID.
|
||||
//----------------------------------------------------------------
|
||||
task tc_get_manufacturer_id;
|
||||
begin : tc_get_id
|
||||
reg [7 : 0] rx_byte;
|
||||
tc_ctr = tc_ctr + 1;
|
||||
monitor = 0;
|
||||
|
||||
$display("");
|
||||
$display("--- tc_get_manufacturer_id: Read out device id from the memory.");
|
||||
|
||||
#(2 * CLK_PERIOD);
|
||||
enable_spi();
|
||||
#(2 * CLK_PERIOD);
|
||||
|
||||
// Send 0x90 command.
|
||||
$display("--- tc_get_manufacturer_id: Sending 0xab command.");
|
||||
xfer_byte(8'h90, rx_byte);
|
||||
|
||||
// Dummy bytes.
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
$display("--- tc_get_manufacturer_id: Got 0x%02x after dummy byte 1", rx_byte);
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
$display("--- tc_get_manufacturer_id: Got 0x%02x after dummy byte 2", rx_byte);
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
$display("--- tc_get_manufacturer_id: Got 0x%02x after dummy byte 3", rx_byte);
|
||||
|
||||
// Get the ID byte.
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
$display("--- tc_get_manufacturer_id: Got ID 0x%02x after dummy byte 4", rx_byte);
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
$display("--- tc_get_manufacturer_id: Got ID 0x%02x after dummy byte 5", rx_byte);
|
||||
|
||||
disable_spi();
|
||||
#(2 * CLK_PERIOD);
|
||||
|
||||
$display("--- tc_get_manufacturer_id: completed.");
|
||||
$display("");
|
||||
end
|
||||
endtask // tc_get_manufacturer_id
|
||||
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// tc_read_mem()
|
||||
//
|
||||
// Test case that reads out the first 16 bytes of the memory.
|
||||
//----------------------------------------------------------------
|
||||
task tc_read_mem;
|
||||
begin : tc_get_id
|
||||
reg [7 : 0] rx_byte;
|
||||
integer i;
|
||||
tc_ctr = tc_ctr + 1;
|
||||
monitor = 0;
|
||||
verbose = 0;
|
||||
|
||||
$display("");
|
||||
$display("--- tc_read_mem: Read out the first 16 bytes from the memory.");
|
||||
|
||||
#(2 * CLK_PERIOD);
|
||||
enable_spi();
|
||||
#(2 * CLK_PERIOD);
|
||||
|
||||
// Send read command 0x03.
|
||||
$display("--- tc_read_mem: Sending 0x03 command.");
|
||||
xfer_byte(8'h03, rx_byte);
|
||||
|
||||
// Send adress 0x000000.
|
||||
$display("--- tc_read_mem: Sending 24 bit address 0x000000.");
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
|
||||
// Read out 16 bytes.
|
||||
$display("--- tc_read_mem: Reading out 16 bytes from the memory.");
|
||||
for (i = 1 ; i < 17 ; i = i + 1) begin
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
$display("--- tc_read_mem: Byte %d: 0x%02x", i, rx_byte);
|
||||
end
|
||||
|
||||
disable_spi();
|
||||
#(2 * CLK_PERIOD);
|
||||
|
||||
$display("--- tc_read_mem: completed.");
|
||||
$display("");
|
||||
end
|
||||
endtask // tc_read_mem
|
||||
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// tc_rmr_mem()
|
||||
//
|
||||
// Test case that reads out the first 16 bytes of the memory,
|
||||
// erase the same area, reads out the contents again, writes
|
||||
// a known pattern and the reads it out again.
|
||||
//----------------------------------------------------------------
|
||||
task tc_rmr_mem;
|
||||
begin : tc_get_id
|
||||
reg [7 : 0] rx_byte;
|
||||
integer i;
|
||||
tc_ctr = tc_ctr + 1;
|
||||
monitor = 0;
|
||||
verbose = 0;
|
||||
|
||||
$display("");
|
||||
$display("--- tc_rmr_mem: Read out the first 16 bytes from the memory.");
|
||||
read_mem_range(24'h000000, 16);
|
||||
|
||||
$display("");
|
||||
$display("--- tc_rmr_mem: Status before write enable:");
|
||||
read_status();
|
||||
|
||||
// Set write enable mode.
|
||||
enable_spi();
|
||||
// #(2 * CLK_PERIOD);
|
||||
xfer_byte(8'h06, rx_byte);
|
||||
// #(2 * CLK_PERIOD);
|
||||
disable_spi();
|
||||
#(2 * CLK_PERIOD);
|
||||
$display("--- tc_rmr_mem: Status after write enable:");
|
||||
read_status();
|
||||
|
||||
// Erase sector. Command 0x20 followed by 24 bit address.
|
||||
enable_spi();
|
||||
#(2 * CLK_PERIOD);
|
||||
xfer_byte(8'h20, rx_byte);
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
xfer_byte(8'h00, rx_byte);
|
||||
disable_spi();
|
||||
#(4096 * CLK_PERIOD);
|
||||
$display("--- tc_rmr_mem: Content of memory after erase.");
|
||||
read_mem_range(24'h000000, 16);
|
||||
|
||||
disable_spi();
|
||||
#(2 * CLK_PERIOD);
|
||||
|
||||
$display("--- tc_rmr_mem: completed.");
|
||||
$display("");
|
||||
end
|
||||
endtask // tc_rmr_mem
|
||||
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// tk1_spi_master_test
|
||||
//----------------------------------------------------------------
|
||||
initial
|
||||
begin : tk1_spi_master_test
|
||||
$display("");
|
||||
$display(" -= Testbench for tk1_spi_master started =-");
|
||||
$display(" =======================================");
|
||||
$display("");
|
||||
|
||||
init_sim();
|
||||
reset_dut();
|
||||
disable_spi();
|
||||
|
||||
verbose = 1;
|
||||
|
||||
// tc_get_device_id();
|
||||
tc_get_jedec_id();
|
||||
// tc_get_manufacturer_id();
|
||||
tc_get_unique_device_id();
|
||||
tc_read_mem();
|
||||
// tc_rmr_mem();
|
||||
|
||||
display_test_result();
|
||||
$display("");
|
||||
$display(" -= Testbench for tk1_spi_master completed =-");
|
||||
$display(" =========================================");
|
||||
$display("");
|
||||
$finish;
|
||||
end // tk1_spi_master_test
|
||||
endmodule // tb_tk1_spi_master
|
||||
|
||||
//======================================================================
|
||||
// EOF tb_tk1_spi_master.v
|
||||
//======================================================================
|
||||
|
|
@ -11,7 +11,11 @@
|
|||
#
|
||||
#===================================================================
|
||||
|
||||
TOP_SRC=../rtl/tk1.v
|
||||
SPI_SRC=../rtl/tk1_spi_master.v
|
||||
TB_SPI_SRC =../tb/tb_tk1_spi_master.v
|
||||
MEM_MODEL_SRC =../tb/W25Q80DL.v
|
||||
|
||||
TOP_SRC=../rtl/tk1.v $(SPI_SRC)
|
||||
TB_TOP_SRC =../tb/tb_tk1.v ../tb/sb_rgba_drv.v
|
||||
|
||||
CC = iverilog
|
||||
|
|
@ -21,11 +25,23 @@ LINT = verilator
|
|||
LINT_FLAGS = +1364-2005ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
|
||||
|
||||
|
||||
all: top.sim
|
||||
all: MEM.TXT spi.sim top.sim
|
||||
|
||||
|
||||
MEM.TXT:
|
||||
../tools/mem_gen.py > MEM.TXT
|
||||
|
||||
|
||||
spi.sim: $(TB_SPI_SRC) $(SPI_SRC) $(MEM_MODEL_SRC)
|
||||
$(CC) $(CC_FLAGS) -o spi.sim $^
|
||||
|
||||
|
||||
top.sim: $(TB_TOP_SRC) $(TOP_SRC)
|
||||
$(CC) $(CC_FLAGS) -o top.sim $(TB_TOP_SRC) $(TOP_SRC) -DUDI_HEX=\"../tb/udi.hex\"
|
||||
$(CC) $(CC_FLAGS) -o top.sim $^ -DUDI_HEX=\"../tb/udi.hex\"
|
||||
|
||||
|
||||
sim-spi: spi.sim
|
||||
./spi.sim
|
||||
|
||||
|
||||
sim-top: top.sim
|
||||
|
|
@ -33,7 +49,7 @@ sim-top: top.sim
|
|||
|
||||
|
||||
lint-top: $(TOP_SRC)
|
||||
$(LINT) $(LINT_FLAGS) $(TOP_SRC)
|
||||
$(LINT) $(LINT_FLAGS) $^ ../tb/sb_rgba_drv.v -DUDI_HEX=\"../tb/udi.hex\"
|
||||
|
||||
|
||||
lint-spi: $(SPI_SRC)
|
||||
|
|
@ -41,14 +57,17 @@ lint-spi: $(SPI_SRC)
|
|||
|
||||
|
||||
clean:
|
||||
rm -f spi.sim
|
||||
rm -f top.sim
|
||||
|
||||
rm -f MEM.TXT
|
||||
|
||||
help:
|
||||
@echo "Build system for simulation of TK1 core"
|
||||
@echo ""
|
||||
@echo "Supported targets:"
|
||||
@echo "------------------"
|
||||
@echo "spi.sim: Build SPI simulation target."
|
||||
@echo "sim-spi: Run SPI simulation."
|
||||
@echo "top.sim: Build top level simulation target."
|
||||
@echo "sim-top: Run top level simulation."
|
||||
@echo "lint-top: Lint top rtl source files."
|
||||
|
|
|
|||
|
|
@ -0,0 +1,19 @@
|
|||
#!/usr/bin/env python3
|
||||
# -*- coding: utf-8 -*-
|
||||
#=======================================================================
|
||||
#
|
||||
# mem_gen.py
|
||||
# ------
|
||||
# Program that generates hex memory file read by the memory model.
|
||||
#
|
||||
# Copyright (C) 2024 - Tillitis AB
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
# print("// Memory data loaded into the module at init.")
|
||||
for i in range(int(16793600 / 4)):
|
||||
print("de")
|
||||
print("ad")
|
||||
print("be")
|
||||
print("ef")
|
||||
Loading…
Reference in New Issue