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fpga: Include SPI master during linting

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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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Joachim Strömbergson 2024-07-09 13:24:04 +02:00 committed by Daniel Jobson
parent 41e63e6e42
commit fdb7604286
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GPG Key ID: 3707A9DBF4BB8F1A
1 changed files with 1 additions and 0 deletions
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hw/application_fpga/Makefile
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@ -199,6 +199,7 @@ LINT_FLAGS = +1364-2005ext+ --lint-only \
lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS) lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS)
$(LINT) $(LINT_FLAGS) \ $(LINT) $(LINT_FLAGS) \
-DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \ -DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
-DINCLUDE_SPI_MASTER \
-DFIRMWARE_HEX=\"$(P)/firmware.hex\" \ -DFIRMWARE_HEX=\"$(P)/firmware.hex\" \
-DUDS_HEX=\"$(P)/data/uds.hex\" \ -DUDS_HEX=\"$(P)/data/uds.hex\" \
-DUDI_HEX=\"$(P)/data/udi.hex\" \ -DUDI_HEX=\"$(P)/data/udi.hex\" \