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FPGA: Increase UART baud rate to 500k

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Mikael Ågren 2024-10-09 09:45:29 +02:00 committed by Michael Cardell Widerkrantz
parent 195fbb7699
commit facde9c1a0
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GPG Key ID: D3DB3DDF57E704E5
1 changed files with 3 additions and 3 deletions
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hw/application_fpga/core/uart/rtl/uart.v
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@ -79,10 +79,10 @@ module uart (
// The default bit rate is based on target clock frequency
// divided by the bit rate times in order to hit the
// center of the bits. I.e.
// Clock: 21 MHz, 62500 bps
// Divisor = 21E6 / 62500 = 336
// Clock: 21 MHz, 500 kbps
// Divisor = 21E6 / 500E3 = 42
// This also satisfies 1E6 % bps == 0 for the CH552 MCU used for USB-serial
localparam DEFAULT_BIT_RATE = 16'd336;
localparam DEFAULT_BIT_RATE = 16'd42;
localparam DEFAULT_DATA_BITS = 4'h8;
localparam DEFAULT_STOP_BITS = 2'h1;