ci: Include Verilog formatting check in CI

- Change checkfmt make target to run both Verilog formatting check and
  C code formatting check.

- Make check formatting it's own job in the CI.

.github/workflows/ci.yaml

@@ -10,7 +10,7 @@ on:
   workflow_dispatch: {}
 
 jobs:
-  check-firmware:
+  check-formatting:
     runs-on: ubuntu-latest
     container:
       image: ghcr.io/tillitis/tkey-builder:5rc1
@@ -26,11 +26,26 @@ jobs:
         run: |
           git config --global --add safe.directory "$GITHUB_WORKSPACE"
 
-      - name: check indentation in firmware C code
+      - name: check formatting on Verilog and C
         working-directory: hw/application_fpga
         run: |
-          make -C fw/tk1 checkfmt
+          make checkfmt
-          make -C fw/testfw checkfmt
+
+  check-firmware:
+    runs-on: ubuntu-latest
+    container:
+      image: ghcr.io/tillitis/tkey-builder:5rc1
+    steps:
+      - name: checkout
+        uses: actions/checkout@v4
+        with:
+          # fetch-depth: 0
+          persist-credentials: false
+
+      - name: fix
+        # https://github.com/actions/runner-images/issues/6775
+        run: |
+          git config --global --add safe.directory "$GITHUB_WORKSPACE"
 
       - name: run static analysis on firmware C code
         working-directory: hw/application_fpga

hw/application_fpga/Makefile

@@ -304,6 +304,8 @@ fmt: $(FPGA_VERILOG_SRCS) $(SIM_VERILOG_SRCS) $(VERILATOR_VERILOG_SRCS) $(VERILO
 # Temporary fix using grep, since the verible with --verify flag only returns
 # error if the last file is malformatted.
 checkfmt: $(FPGA_VERILOG_SRCS) $(SIM_VERILOG_SRCS) $(VERILATOR_VERILOG_SRCS) $(VERILOG_SRCS)
+	make -C fw/tk1 checkfmt
+	make -C fw/testfw checkfmt
 	$(FORMAT) $(CHECK_FORMAT_FLAGS) $^ 2>&1 | \
 		grep "Needs formatting" && exit 1 || true
 .PHONY: checkfmt