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FPGA: Increase SPI speed

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- Change SPI clock from 16 CPU cyles/flank to one cycle/flank
- Remove separate flank length wait states in the FSM

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2024-06-18 11:58:32 +02:00 committed by dehanj
parent 8ce07683f8
commit ec77b15eb8
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GPG Key ID: 3707A9DBF4BB8F1A
1 changed files with 9 additions and 27 deletions
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24
hw/application_fpga/core/tk1/rtl/tk1_spi_master.v
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@ -47,12 +47,10 @@ module tk1_spi_master(
//----------------------------------------------------------------
localparam CTRL_IDLE = 3'h0;
localparam CTRL_POS_FLANK = 3'h1;
localparam CTRL_WAIT_POS = 3'h2;
localparam CTRL_NEG_FLANK = 3'h3;
localparam CTRL_WAIT_NEG = 3'h4;
localparam CTRL_NEXT = 3'h5;
localparam CTRL_NEG_FLANK = 3'h2;
localparam CTRL_NEXT = 3'h3;
localparam SPI_CLK_CYCLES = 4'hf;
localparam SPI_CLK_CYCLES = 4'h1;
//----------------------------------------------------------------
@ -289,32 +287,16 @@ module tk1_spi_master(
spi_rx_data_nxt = 1'h1;
spi_csk_new = 1'h1;
spi_csk_we = 1'h1;
spi_clk_ctr_rst = 1'h1;
spi_ctrl_new = CTRL_WAIT_POS;
spi_ctrl_we = 1'h1;
end
CTRL_WAIT_POS: begin
if (spi_clk_cycles_reached) begin
spi_ctrl_new = CTRL_NEG_FLANK;
spi_ctrl_we = 1'h1;
end
end
CTRL_NEG_FLANK: begin
spi_csk_new = 1'h0;
spi_csk_we = 1'h1;
spi_clk_ctr_rst = 1'h1;
spi_ctrl_new = CTRL_WAIT_NEG;
spi_ctrl_we = 1'h1;
end
CTRL_WAIT_NEG: begin
if (spi_clk_cycles_reached) begin
spi_ctrl_new = CTRL_NEXT;
spi_ctrl_we = 1'h1;
end
end
CTRL_NEXT: begin
if (spi_bit_ctr_reg == 3'h7) begin