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Update Verilog version to 2005 for linting

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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2024-04-22 11:07:58 +02:00 committed by dehanj
parent f655196af7
commit e961f46e79
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GPG Key ID: 3707A9DBF4BB8F1A
6 changed files with 7 additions and 7 deletions
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4
hw/application_fpga/core/timer/toolruns/Makefile
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@ -21,7 +21,7 @@ CC = iverilog
CC_FLAGS = -Wall
LINT = verilator
LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
LINT_FLAGS = +1364-2005ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
all: top.sim core.sim
@ -67,7 +67,7 @@ help:
@echo "sim-top: Run top level simulation."
@echo "sim-core: Run core level simulation."
@echo "lint-core: Lint core rtl source files."
@echo "lint-core: Lint top rtl source files."
@echo "lint-top: Lint top rtl source files."
@echo "clean: Delete all built files."
#===================================================================

2
hw/application_fpga/core/tk1/toolruns/Makefile
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@ -18,7 +18,7 @@ CC = iverilog
CC_FLAGS = -Wall
LINT = verilator
LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
LINT_FLAGS = +1364-2005ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
all: top.sim

2
hw/application_fpga/core/touch_sense/toolruns/Makefile
View File

@ -18,7 +18,7 @@ CC = iverilog
CC_FLAGS = -Wall
LINT = verilator
LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
LINT_FLAGS = +1364-2005ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
all: top.sim

2
hw/application_fpga/core/trng/toolruns/Makefile
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@ -18,7 +18,7 @@ CC = iverilog
CC_FLAGS = -Wall
LINT = verilator
LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
LINT_FLAGS = +1364-2005ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
all: top.sim

2
hw/application_fpga/core/uart/toolruns/Makefile
View File

@ -18,7 +18,7 @@ CC = iverilog
CC_FLAGS = -Wall
LINT = verilator
LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
LINT_FLAGS = +1364-2005ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
all: top.sim

2
hw/application_fpga/core/uds/toolruns/Makefile
View File

@ -18,7 +18,7 @@ CC = iverilog
CC_FLAGS = -Wall
LINT = verilator
LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
LINT_FLAGS = +1364-2005ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
all: top.sim