Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2025-07-26 08:25:31 -04:00
Code Issues Projects Releases Packages Wiki Activity

Update Verilog version to 2005 for linting

Browse source 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2024-04-22 11:07:58 +02:00 • committed by dehanj
parent f655196af7
commit e961f46e79
No known key found for this signature in database
GPG key ID: 3707A9DBF4BB8F1A
6 changed files with 7 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

4
hw/application_fpga/core/timer/toolruns/Makefile
View file

@ -21,7 +21,7 @@ CC = iverilog
CC_FLAGS = -Wall CC_FLAGS = -Wall
LINT = verilator LINT = verilator
LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME LINT_FLAGS = +1364-2005ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
all: top.sim core.sim all: top.sim core.sim
@ -67,7 +67,7 @@ help:
@echo "sim-top: Run top level simulation." @echo "sim-top: Run top level simulation."
@echo "sim-core: Run core level simulation." @echo "sim-core: Run core level simulation."
@echo "lint-core: Lint core rtl source files." @echo "lint-core: Lint core rtl source files."
@echo "lint-core: Lint top rtl source files." @echo "lint-top: Lint top rtl source files."
@echo "clean: Delete all built files." @echo "clean: Delete all built files."
#=================================================================== #===================================================================

2
hw/application_fpga/core/tk1/toolruns/Makefile
View file

@ -18,7 +18,7 @@ CC = iverilog
CC_FLAGS = -Wall CC_FLAGS = -Wall
LINT = verilator LINT = verilator
LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME LINT_FLAGS = +1364-2005ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
all: top.sim all: top.sim

2
hw/application_fpga/core/touch_sense/toolruns/Makefile
View file

@ -18,7 +18,7 @@ CC = iverilog
CC_FLAGS = -Wall CC_FLAGS = -Wall
LINT = verilator LINT = verilator
LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME LINT_FLAGS = +1364-2005ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
all: top.sim all: top.sim

2
hw/application_fpga/core/trng/toolruns/Makefile
View file

@ -18,7 +18,7 @@ CC = iverilog
CC_FLAGS = -Wall CC_FLAGS = -Wall
LINT = verilator LINT = verilator
LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME LINT_FLAGS = +1364-2005ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
all: top.sim all: top.sim

2
hw/application_fpga/core/uart/toolruns/Makefile
View file

@ -18,7 +18,7 @@ CC = iverilog
CC_FLAGS = -Wall CC_FLAGS = -Wall
LINT = verilator LINT = verilator
LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME LINT_FLAGS = +1364-2005ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
all: top.sim all: top.sim

2
hw/application_fpga/core/uds/toolruns/Makefile
View file

@ -18,7 +18,7 @@ CC = iverilog
CC_FLAGS = -Wall CC_FLAGS = -Wall
LINT = verilator LINT = verilator
LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME LINT_FLAGS = +1364-2005ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
all: top.sim all: top.sim