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Update Verilog version to 2005 for linting

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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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Joachim Strömbergson 2024-04-22 11:07:58 +02:00 • committed by dehanj
parent f655196af7
commit e961f46e79
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6 changed files with 7 additions and 7 deletions
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hw/application_fpga/core/uds/toolruns/Makefile
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@ -18,7 +18,7 @@ CC = iverilog
CC_FLAGS = -Wall
LINT = verilator
LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
LINT_FLAGS = +1364-2005ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
all: top.sim