(fpga) First attempt at PoC of HW trampoline for syscall.

This commit adds a first attempt at adding a HW based syscall
       trampoline. Basicallt the FW can set a fixed address in a
       register in the API. The app can write an API adress. When
       written the HW will (should) force the CPU to read the
       instruction pointed to by the address set by the FW.

       This probably doesn't work. One problem is probably timing
       (cycles between writing the API and loading of the next
       instruction). We need to try.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>

hw/application_fpga/core/tk1/rtl/tk1.v

@@ -26,6 +26,9 @@ module tk1(
 	   output wire          force_trap,
 	   output               system_reset,
 
+	   output wire [31 : 0] syscall_addr,
+	   output wire          syscall,
+
 	   output wire [14 : 0] ram_addr_rand,
 	   output wire [31 : 0] ram_data_rand,
 
@@ -81,6 +84,9 @@ module tk1(
 
   localparam ADDR_BLAKE2S       = 8'h10;
 
+  localparam ADDR_SYSCALL_ADDR  = 8'h12;
+  localparam ADDR_SYSCALL_START = 8'h13;
+
   localparam ADDR_CDI_FIRST     = 8'h20;
   localparam ADDR_CDI_LAST      = 8'h27;
 
@@ -138,6 +144,9 @@ module tk1(
   reg [31 : 0] blake2s_addr_reg;
   reg          blake2s_addr_we;
 
+  reg [31 : 0] syscall_addr_reg;
+  reg          syscall_addr_we;
+
   reg [23 : 0] cpu_trap_ctr_reg;
   reg [23 : 0] cpu_trap_ctr_new;
   reg [2 : 0]  cpu_trap_led_reg;
@@ -175,6 +184,8 @@ module tk1(
 
   wire [31:0]  udi_rdata;
 
+  reg          start_syscall;
+
 `ifdef INCLUDE_SPI_MASTER
   reg          spi_enable;
   reg          spi_enable_vld;
@@ -204,6 +215,9 @@ module tk1(
 
   assign system_reset = system_reset_reg;
 
+  assign syscall_addr = syscall_addr_reg;
+  assign syscall      = start_syscall;
+
 
   //----------------------------------------------------------------
   // Module instance.
@@ -268,6 +282,7 @@ module tk1(
         app_start_reg     <= 32'h0;
         app_size_reg      <= 32'h0;
         blake2s_addr_reg  <= 32'h0;
+        syscall_addr_reg  <= 32'h0;
 	cdi_mem[0]        <= 32'h0;
 	cdi_mem[1]        <= 32'h0;
 	cdi_mem[2]        <= 32'h0;
@@ -326,6 +341,10 @@ module tk1(
           blake2s_addr_reg <= write_data;
         end
 
+        if (syscall_addr_we) begin
+          syscall_addr_reg <= write_data;
+        end
+
 	if (cdi_mem_we) begin
 	  cdi_mem[address[2 : 0]] <= write_data;
 	end
@@ -436,6 +455,8 @@ module tk1(
       app_start_we     = 1'h0;
       app_size_we      = 1'h0;
       blake2s_addr_we  = 1'h0;
+      syscall_addr_we  = 1'h0;
+      start_syscall    = 1'h0;
       cdi_mem_we       = 1'h0;
       cdi_mem_we       = 1'h0;
       ram_addr_rand_we = 1'h0;
@@ -495,6 +516,16 @@ module tk1(
             end
 	  end
 
+          if (address == ADDR_SYSCALL_ADDR) begin
+	    if (!switch_app_reg) begin
+              syscall_addr_we = 1'h1;
+            end
+	  end
+
+          if (address == ADDR_SYSCALL_START) begin
+            start_syscall = 1'h1;
+	  end
+
 	  if ((address >= ADDR_CDI_FIRST) && (address <= ADDR_CDI_LAST)) begin
 	    if (!switch_app_reg) begin
 	      cdi_mem_we = 1'h1;

hw/application_fpga/rtl/application_fpga.v

@@ -149,6 +149,8 @@ module application_fpga(
   wire [14 : 0] ram_addr_rand;
   wire [31 : 0] ram_data_rand;
   wire          tk1_system_reset;
+  wire [31 : 0] tk1_syscall_addr;
+  wire          tk1_syscall;
   /* verilator lint_on UNOPTFLAT */
 
 
@@ -328,6 +330,9 @@ module application_fpga(
 
 	       .system_reset(tk1_system_reset),
 
+	       .syscall_addr(tk1_syscall_addr),
+	       .syscall(tk1_syscall),
+
                .ram_addr_rand(ram_addr_rand),
 	       .ram_data_rand(ram_data_rand),
 
@@ -443,10 +448,16 @@ module application_fpga(
             end
 
             RAM_PREFIX: begin
-	      ram_cs          = 1'h1;
+	      if (tk1_syscall) begin
-	      ram_we          = cpu_wstrb;
+		muxed_rdata_new = tk1_syscall_addr;
-	      muxed_rdata_new = ram_read_data ^ ram_data_rand ^ {2{cpu_addr[15 : 0]}};
+		muxed_ready_new = 1'h1;
-	      muxed_ready_new = ram_ready;
+	      end
+	      else begin
+		ram_cs          = 1'h1;
+		ram_we          = cpu_wstrb;
+		muxed_rdata_new = ram_read_data ^ ram_data_rand ^ {2{cpu_addr[15 : 0]}};
+		muxed_ready_new = ram_ready;
+	      end
 	    end
 
             RESERVED_PREFIX: begin