mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2024-10-01 01:45:38 -04:00
Include SPI master in default build
This commit is contained in:
Jonas Thörnblad
parent
35052e50cb
commit
e625586148
@ -33,11 +33,6 @@ run-make:
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podman run --rm --mount type=bind,source="`pwd`/../hw/application_fpga",target=/build -w /build -it \
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$(IMAGE) make clean application_fpga.bin
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run-make-spi:
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podman run --rm --mount type=bind,source="`pwd`/../hw/application_fpga",target=/build -w /build -it \
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$(IMAGE) make clean application_fpga.bin YOSYS_FLAG=-DINCLUDE_SPI_MASTER
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run-tb:
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podman run --rm --mount type=bind,source="`pwd`/../hw/application_fpga",target=/build -w /build -it \
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$(IMAGE) make tb
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@ -242,13 +242,6 @@ tb:
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#-------------------------------------------------------------------
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# Main FPGA build flow.
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# Synthesis. Place & Route. Bitstream generation.
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#
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# To include the SPI-master, add the flag -DINCLUDE_SPI_MASTER to Yosys cmd.
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# This can, for example, be done using
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# 'make application_fpga.bin YOSYS_FLAG=-DINCLUDE_SPI_MASTER'.
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# Important: do a make clean between builds with and wihtout the SPI master.
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# Otherwise, there is a risk of unintended components persisting between
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# builds.
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#-------------------------------------------------------------------
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YOSYS_FLAG ?=
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@ -29,12 +29,10 @@ module tk1(
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output wire [14 : 0] ram_addr_rand,
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output wire [31 : 0] ram_data_rand,
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`ifdef INCLUDE_SPI_MASTER
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output wire spi_ss,
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output wire spi_sck,
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output wire spi_mosi,
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input wire spi_miso,
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`endif // INCLUDE_SPI_MASTER
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output wire led_r,
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output wire led_g,
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@ -96,11 +94,9 @@ module tk1(
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localparam ADDR_SYSTEM_RESET = 8'h70;
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`ifdef INCLUDE_SPI_MASTER
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localparam ADDR_SPI_EN = 8'h80;
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localparam ADDR_SPI_XFER = 8'h81;
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localparam ADDR_SPI_DATA = 8'h82;
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`endif // INCLUDE_SPI_MASTER
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localparam TK1_NAME0 = 32'h746B3120; // "tk1 "
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localparam TK1_NAME1 = 32'h6d6b6466; // "mkdf"
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@ -175,7 +171,6 @@ module tk1(
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wire [31:0] udi_rdata;
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`ifdef INCLUDE_SPI_MASTER
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reg spi_enable;
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reg spi_enable_vld;
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reg spi_start;
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@ -183,8 +178,6 @@ module tk1(
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reg spi_tx_data_vld;
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wire spi_ready;
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wire [7 : 0] spi_rx_data;
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`endif // INCLUDE_SPI_MASTER
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//----------------------------------------------------------------
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// Concurrent connectivity for ports etc.
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@ -226,7 +219,6 @@ module tk1(
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);
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/* verilator lint_on PINMISSING */
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`ifdef INCLUDE_SPI_MASTER
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tk1_spi_master spi_master(
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.clk(clk),
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.reset_n(reset_n),
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@ -244,8 +236,6 @@ module tk1(
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.spi_rx_data(spi_rx_data),
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.spi_ready(spi_ready)
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);
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`endif // INCLUDE_SPI_MASTER
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udi_rom rom_i(
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.addr(address[0]),
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@ -448,14 +438,12 @@ module tk1(
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tmp_read_data = 32'h0;
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tmp_ready = 1'h0;
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`ifdef INCLUDE_SPI_MASTER
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spi_enable_vld = 1'h0;
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spi_start = 1'h0;
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spi_tx_data_vld = 1'h0;
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spi_enable = write_data[0];
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spi_tx_data = write_data[7 : 0];
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`endif // INCLUDE_SPI_MASTER
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if (cs) begin
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tmp_ready = 1'h1;
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@ -529,7 +517,6 @@ module tk1(
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end
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end
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`ifdef INCLUDE_SPI_MASTER
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if (address == ADDR_SPI_EN) begin
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spi_enable_vld = 1'h1;
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end
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@ -541,7 +528,6 @@ module tk1(
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if (address == ADDR_SPI_DATA) begin
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spi_tx_data_vld = 1'h1;
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end
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`endif // INCLUDE_SPI_MASTER
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end
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else begin
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@ -592,7 +578,6 @@ module tk1(
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end
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end
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`ifdef INCLUDE_SPI_MASTER
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if (address == ADDR_SPI_XFER) begin
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tmp_read_data[0] = spi_ready;
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end
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@ -600,7 +585,6 @@ module tk1(
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if (address == ADDR_SPI_DATA) begin
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tmp_read_data[7 : 0] = spi_rx_data;
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end
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`endif // INCLUDE_SPI_MASTER
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end
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end
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@ -38,7 +38,7 @@ spi.sim: $(TB_SPI_SRC) $(SPI_SRC) $(MEM_MODEL_SRC)
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top.sim: $(TB_TOP_SRC) $(TOP_SRC)
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$(CC) $(CC_FLAGS) -o top.sim $^ -DUDI_HEX=\"../tb/udi.hex\" -DINCLUDE_SPI_MASTER
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$(CC) $(CC_FLAGS) -o top.sim $^ -DUDI_HEX=\"../tb/udi.hex\"
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sim-spi: spi.sim
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@ -50,7 +50,7 @@ sim-top: top.sim
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lint-top: $(LINT_SRC)
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$(LINT) $(LINT_FLAGS) $^ -DUDI_HEX=\"../tb/udi.hex\" -DINCLUDE_SPI_MASTER
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$(LINT) $(LINT_FLAGS) $^ -DUDI_HEX=\"../tb/udi.hex\"
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clean:
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@ -20,12 +20,10 @@ module application_fpga(
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output wire interface_rx,
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input wire interface_tx,
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`ifdef INCLUDE_SPI_MASTER
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output wire spi_ss,
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output wire spi_sck,
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output wire spi_mosi,
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input wire spi_miso,
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`endif // INCLUDE_SPI_MASTER
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input wire touch_event,
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@ -334,12 +332,10 @@ module application_fpga(
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.ram_addr_rand(ram_addr_rand),
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.ram_data_rand(ram_data_rand),
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`ifdef INCLUDE_SPI_MASTER
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.spi_ss(spi_ss),
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.spi_sck(spi_sck),
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.spi_mosi(spi_mosi),
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.spi_miso(spi_miso),
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`endif // INCLUDE_SPI_MASTER
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.led_r(led_r),
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.led_g(led_g),
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