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Document FW_RAM and CDI computation
This commit is contained in:
Michael Cardell Widerkrantz
Daniel Lublin
parent
c851b2c0b1
commit
e53811ca91
@ -37,8 +37,8 @@ application mode. The firmware mode has the responsibility of
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receiving, measuring, and loading the application.
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The firmware and application uses a memory mapped IO for SoC
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communication. This MMIO resides at `0xc000_0000`. *Nota bene*: All
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access to MMIO should be word (32 bit) aligned.
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communication. This MMIO resides at `0xc000_0000`. *Nota bene*: Almost
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all access to MMIO should be word (32 bit) aligned. See table below.
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The application has a constrained variant of the firmware memory map,
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which is outlined below. E.g. UDS isn't readable, and the `APP_{ADDR,
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@ -117,6 +117,26 @@ to check application image is sane. The shared firmware data area
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(e.g. `.data` and the stack must be cleared prior launching the
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application.
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### CDI computation
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The CDI is computed by:
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```
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CDI = blake2s(UDS, blake2s(app), USS)
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```
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In an ideal world, software would never be able to read UDS at all and
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we would have a BLAKE2s function in hardware that would be the only
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thing able to read the UDS. Unfortunately, we couldn't fit a BLAKE2s
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implementation in the FPGA at this time.
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The firmware instead does the CDI computation using the special
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firmware-only `FW_RAM` which is invisible after switching to app mode.
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The `blake2s()` function in the firmware is fed with a buffer in
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`FW_RAM` containing the UDS, the app digest, and the USS. It is also
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fed with a context used for computations that is also part of the
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`FW_RAM`.
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### Loading the User Supplied Secret (USS)
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The host program may send `FW_CMD_LOAD_USS` and `FW_CMD_LOAD_APP_SIZE`
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@ -299,43 +319,44 @@ Assigned core prefixes:
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| UDS | 0xc2 |
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| UART | 0xc3 |
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| TOUCH | 0xc4 |
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| FW_RAM | 0xd0 |
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| MTA1 | 0xff |
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| | |
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*Nota bene*: MMIO accesses should be 32 bit wide, e.g use `lw` and
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`sw`. Exceptions are `FW_RAM` and `QEMU_DEBUG`.
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*Nota bene*: All MMIO accesses should be 32 bit wide, e.g use `lw` and `sw`.
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| *name* | *fw* | *app | *size* | *type* | *content* | *description* |
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|--------------------|------|------------|--------|---------|-----------|-----------------------------------------------------------------------|
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| `TRNG_STATUS` | r | r | | | | STATUS_READY_BIT is set when an entropy word is available. |
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| `TRNG_ENTROPY` | r | r | 4B | u32 | | Entropy word. Reading a word will clear status. |
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| `TIMER_CTRL` | r/w | r/w | | | | If bit 0 in TIMER_STATUS is set then writing here starts the timer. |
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| | | | | | | If bit 0 in TIMER_STATUS is unset then writing here stops the timer. |
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| `TIMER_STATUS` | r | r | | | | If bit 0 is set, the timer is ready to start running. |
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| `TIMER_PRESCALER` | r/w | r/w | 4B | | | Prescaler init value. Write blocked when running. |
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| `TIMER_TIMER` | r/w | r/w | 4B | | | Timer init or current value when running. Write blocked when running. |
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| `UDS_FIRST` | r[^3]| invisible | 4B | u8[32] | | First word of Unique Device Secret key. |
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| `UDS_LAST` | | invisible | | | | The last word of the UDS |
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| `UART_BITRATE` | r/w | | | | | TBD |
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| `UART_DATABITS` | r/w | | | | | TBD |
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| `UART_STOPBITS` | r/w | | | | | TBD |
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| `UART_RX_STATUS` | r | r | 1B | u8 | | Non-zero when there is data to read |
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| `UART_RX_DATA` | r | r | 1B | u8 | | Data to read. Only LSB contains data |
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| `UART_TX_STATUS` | r | r | 1B | u8 | | Non-zero when it's OK to write data |
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| `UART_TX_DATA` | w | w | 1B | u8 | | Data to send. Only LSB contains data |
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| `TOUCH_STATUS` | r/w | r/w | | | | STATUS_EVENT_BIT is set when touched; write to it after |
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| `UDA` | r | invisible | 16B | u8[16] | | Unique Device Authentication key. |
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| `UDI` | r | r | 8B | u64 | | Unique Device ID (UDI). |
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| `QEMU_DEBUG` | w | w | | u8 | | Debug console (only in QEMU) |
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| `NAME0` | r | r | 4B | char[4] | "mta1" | ID of core/stick |
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| `NAME1` | r | r | 4B | char[4] | "mkdf" | ID of core/stick |
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| `VERSION` | r | r | 4B | u32 | 1 | Current version. |
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| `SWITCH_APP` | w | invisible? | 1B | u8 | | Switch to application mode. Write non-zero to trigger. |
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| `LED` | w | w | 1B | u8 | | |
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| `GPIO` | | | | | | |
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| `APP_ADDR` | r/w | r | 4B | u32 | | Application address (0x4000_0000) |
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| `APP_SIZE` | r/w | r | 4B | u32 | | Application size |
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| `CDI_FIRST` | r/w | r | 32B | u8[32] | | Compound Device Identifier (CDI). UDS+measurement... |
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| `CDI_LAST` | | r | | | | Last word of CDI |
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| *name* | *fw* | *app | *size* | *type* | *content* | *description* |
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|-------------------|-------|------------|--------|----------|-----------|-----------------------------------------------------------------------|
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| `TRNG_STATUS` | r | r | | | | STATUS_READY_BIT is set when an entropy word is available. |
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| `TRNG_ENTROPY` | r | r | 4B | u32 | | Entropy word. Reading a word will clear status. |
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| `TIMER_CTRL` | r/w | r/w | | | | If bit 0 in TIMER_STATUS is set then writing here starts the timer. |
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| | | | | | | If bit 0 in TIMER_STATUS is unset then writing here stops the timer. |
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| `TIMER_STATUS` | r | r | | | | If bit 0 is set, the timer is ready to start running. |
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| `TIMER_PRESCALER` | r/w | r/w | 4B | | | Prescaler init value. Write blocked when running. |
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| `TIMER_TIMER` | r/w | r/w | 4B | | | Timer init or current value when running. Write blocked when running. |
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| `UDS_FIRST` | r[^3] | invisible | 4B | u8[32] | | First word of Unique Device Secret key. |
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| `UDS_LAST` | | invisible | | | | The last word of the UDS |
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| `UART_BITRATE` | r/w | | | | | TBD |
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| `UART_DATABITS` | r/w | | | | | TBD |
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| `UART_STOPBITS` | r/w | | | | | TBD |
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| `UART_RX_STATUS` | r | r | 1B | u8 | | Non-zero when there is data to read |
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| `UART_RX_DATA` | r | r | 1B | u8 | | Data to read. Only LSB contains data |
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| `UART_TX_STATUS` | r | r | 1B | u8 | | Non-zero when it's OK to write data |
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| `UART_TX_DATA` | w | w | 1B | u8 | | Data to send. Only LSB contains data |
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| `TOUCH_STATUS` | r/w | r/w | | | | STATUS_EVENT_BIT is set when touched; write to it after |
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| `FW_RAM` | r/w | invisible | 1 kiB | u8[1024] | | Firmware-only RAM. |
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| `UDA` | r | invisible | 16B | u8[16] | | Unique Device Authentication key. |
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| `UDI` | r | r | 8B | u64 | | Unique Device ID (UDI). |
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| `QEMU_DEBUG` | w | w | | u8 | | Debug console (only in QEMU) |
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| `NAME0` | r | r | 4B | char[4] | "mta1" | ID of core/stick |
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| `NAME1` | r | r | 4B | char[4] | "mkdf" | ID of core/stick |
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| `VERSION` | r | r | 4B | u32 | 1 | Current version. |
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| `SWITCH_APP` | w | invisible? | 1B | u8 | | Switch to application mode. Write non-zero to trigger. |
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| `LED` | w | w | 1B | u8 | | |
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| `GPIO` | | | | | | |
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| `APP_ADDR` | r/w | r | 4B | u32 | | Application address (0x4000_0000) |
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| `APP_SIZE` | r/w | r | 4B | u32 | | Application size |
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| `CDI_FIRST` | r/w | r | 32B | u8[32] | | Compound Device Identifier (CDI). UDS+measurement... |
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| `CDI_LAST` | | r | | | | Last word of CDI |
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[^3]: The UDS can only be read *once* per power-cycle.
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