From de668a0244d76ebbda6b839dfb4bdb5da1f96589 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Tue, 19 Mar 2024 14:48:52 +0100 Subject: [PATCH] Clean up code and silence warnings after linting MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Joachim Strömbergson --- hw/application_fpga/core/tk1/rtl/tk1.v | 2 ++ hw/application_fpga/core/trng/rtl/rosc.v | 5 +++-- hw/application_fpga/rtl/application_fpga.v | 22 +++++--------------- hw/application_fpga/rtl/rom.v | 24 +++++++++++++++++----- 4 files changed, 29 insertions(+), 24 deletions(-) diff --git a/hw/application_fpga/core/tk1/rtl/tk1.v b/hw/application_fpga/core/tk1/rtl/tk1.v index c3d1534..bd45642 100644 --- a/hw/application_fpga/core/tk1/rtl/tk1.v +++ b/hw/application_fpga/core/tk1/rtl/tk1.v @@ -61,8 +61,10 @@ module tk1( localparam LED_B_BIT = 0; localparam ADDR_GPIO = 8'h0a; + /* verilator lint_off UNUSED */ localparam GPIO1_BIT = 0; localparam GPIO2_BIT = 1; + /* verilator lint_on UNUSED */ localparam GPIO3_BIT = 2; localparam GPIO4_BIT = 3; diff --git a/hw/application_fpga/core/trng/rtl/rosc.v b/hw/application_fpga/core/trng/rtl/rosc.v index 3e7ff51..52e1439 100644 --- a/hw/application_fpga/core/trng/rtl/rosc.v +++ b/hw/application_fpga/core/trng/rtl/rosc.v @@ -36,7 +36,6 @@ module rosc( //---------------------------------------------------------------- // API localparam ADDR_STATUS = 8'h09; - localparam STATUS_READY_BIT = 0; localparam ADDR_ENTROPY = 8'h20; // Total number of ROSCs will be 2 x NUM_ROSC. @@ -115,10 +114,12 @@ module rosc( for(i = 0 ; i < NUM_ROSC ; i = i + 1) begin: oscillators /* verilator lint_off PINMISSING */ + /* verilator lint_off UNOPTFLAT */ (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv_f (.I0(f[i]), .O(f[i])); (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv_g (.I0(g[i]), .O(g[i])); - /* verilator lint_off PINMISSING */ + /* verilator lint_on UNOPTFLAT */ + /* verilator lint_on PINMISSING */ end endgenerate diff --git a/hw/application_fpga/rtl/application_fpga.v b/hw/application_fpga/rtl/application_fpga.v index 91a6efb..4f8b5e5 100644 --- a/hw/application_fpga/rtl/application_fpga.v +++ b/hw/application_fpga/rtl/application_fpga.v @@ -71,18 +71,16 @@ module application_fpga( wire clk; wire reset_n; + /* verilator lint_off UNOPTFLAT */ wire cpu_trap; wire cpu_valid; wire cpu_instr; wire [03 : 0] cpu_wstrb; /* verilator lint_off UNUSED */ wire [31 : 0] cpu_addr; - /* verilator lint_on UNUSED */ wire [31 : 0] cpu_wdata; - /* verilator lint_off UNOPTFLAT */ reg rom_cs; - /* verilator lint_on UNOPTFLAT */ reg [11 : 0] rom_address; wire [31 : 0] rom_read_data; wire rom_ready; @@ -94,60 +92,46 @@ module application_fpga( wire [31 : 0] ram_read_data; wire ram_ready; - /* verilator lint_off UNOPTFLAT */ reg trng_cs; - /* verilator lint_on UNOPTFLAT */ reg trng_we; reg [7 : 0] trng_address; reg [31 : 0] trng_write_data; wire [31 : 0] trng_read_data; wire trng_ready; - /* verilator lint_off UNOPTFLAT */ reg timer_cs; - /* verilator lint_on UNOPTFLAT */ reg timer_we; reg [7 : 0] timer_address; reg [31 : 0] timer_write_data; wire [31 : 0] timer_read_data; wire timer_ready; - /* verilator lint_off UNOPTFLAT */ reg uds_cs; - /* verilator lint_on UNOPTFLAT */ reg [2 : 0] uds_address; wire [31 : 0] uds_read_data; wire uds_ready; - /* verilator lint_off UNOPTFLAT */ reg uart_cs; - /* verilator lint_on UNOPTFLAT */ reg uart_we; reg [7 : 0] uart_address; reg [31 : 0] uart_write_data; wire [31 : 0] uart_read_data; wire uart_ready; - /* verilator lint_off UNOPTFLAT */ reg fw_ram_cs; - /* verilator lint_on UNOPTFLAT */ reg [3 : 0] fw_ram_we; reg [8 : 0] fw_ram_address; reg [31 : 0] fw_ram_write_data; wire [31 : 0] fw_ram_read_data; wire fw_ram_ready; - /* verilator lint_off UNOPTFLAT */ reg touch_sense_cs; - /* verilator lint_on UNOPTFLAT */ reg touch_sense_we; reg [7 : 0] touch_sense_address; wire [31 : 0] touch_sense_read_data; wire touch_sense_ready; - /* verilator lint_off UNOPTFLAT */ reg tk1_cs; - /* verilator lint_on UNOPTFLAT */ reg tk1_we; reg [7 : 0] tk1_address; reg [31 : 0] tk1_write_data; @@ -157,6 +141,7 @@ module application_fpga( wire force_trap; wire [14 : 0] ram_aslr; wire [31 : 0] ram_scramble; + /* verilator lint_on UNOPTFLAT */ //---------------------------------------------------------------- @@ -211,6 +196,9 @@ module application_fpga( rom rom_inst( + .clk(clk), + .reset_n(reset_n), + .cs(rom_cs), .address(rom_address), .read_data(rom_read_data), diff --git a/hw/application_fpga/rtl/rom.v b/hw/application_fpga/rtl/rom.v index ee79347..00d0a25 100644 --- a/hw/application_fpga/rtl/rom.v +++ b/hw/application_fpga/rtl/rom.v @@ -15,6 +15,9 @@ `default_nettype none module rom( + input wire clk, + input wire reset_n, + input wire cs, /* verilator lint_off UNUSED */ input wire [11 : 0] address, @@ -42,15 +45,28 @@ module rom( initial $readmemh(`FIRMWARE_HEX, memory); reg [31 : 0] rom_rdata; - - reg rom_ready; + reg ready_reg; //---------------------------------------------------------------- // Concurrent assignments of ports. //---------------------------------------------------------------- assign read_data = rom_rdata; - assign ready = rom_ready; + assign ready = ready_reg; + + + //---------------------------------------------------------------- + // reg_update + //---------------------------------------------------------------- + always @ (posedge clk) + begin : reg_update + if (!reset_n) begin + ready_reg <= 1'h0; + end + else begin + ready_reg <= cs; + end + end // reg_update //---------------------------------------------------------------- @@ -58,11 +74,9 @@ module rom( //---------------------------------------------------------------- always @* begin : rom_logic - /* verilator lint_off WIDTH */ rom_rdata = memory[address]; /* verilator lint_on WIDTH */ - rom_ready = cs; end endmodule // rom