From de4db95bb0d170b6b21dc3e742292de70bb036c4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= <joachim@assured.se>
Date: Thu, 15 Aug 2024 11:29:30 +0200
Subject: [PATCH] (fpga) Fix counting, add make test case self testing.
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       Fix so that the timer counts the correct number of cycles
       (again).

       Make testbench self-testing.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
---
 .../core/timer/rtl/timer_core.v               | 38 ++++--------
 .../core/timer/tb/tb_timer_core.v             | 59 ++++++++++++++++---
 2 files changed, 61 insertions(+), 36 deletions(-)

diff --git a/hw/application_fpga/core/timer/rtl/timer_core.v b/hw/application_fpga/core/timer/rtl/timer_core.v
index 7d3eb83..9830dba 100644
--- a/hw/application_fpga/core/timer/rtl/timer_core.v
+++ b/hw/application_fpga/core/timer/rtl/timer_core.v
@@ -175,9 +175,17 @@ module timer_core(
 	  end
 
 	  else begin
-	    if (prescaler_reg == prescaler_init) begin
-              core_ctrl_new = CTRL_TIMER;
-              core_ctrl_we  = 1'h1;
+	    if (prescaler_reg == (prescaler_init - 1)) begin
+	      if ((timer_reg == (timer_init - 1)) & ~free_running) begin
+		running_new   = 1'h0;
+		running_we    = 1'h1;
+		core_ctrl_new = CTRL_IDLE;
+		core_ctrl_we  = 1'h1;
+	      end
+	      else begin
+		timer_inc     = 1'h1;
+		prescaler_rst = 1'h1;
+	      end
 	    end
 	    else begin
 	      prescaler_inc = 1'h1;
@@ -185,30 +193,6 @@ module timer_core(
 	  end
 	end
 
-
-	CTRL_TIMER: begin
-	  if (stop) begin
-            running_new   = 1'h0;
-            running_we    = 1'h1;
-            core_ctrl_new = CTRL_IDLE;
-            core_ctrl_we  = 1'h1;
-	  end
-	  else begin
-	    if ((timer_reg == timer_init) & ~free_running) begin
-              running_new   = 1'h0;
-              running_we    = 1'h1;
-              core_ctrl_new = CTRL_IDLE;
-              core_ctrl_we  = 1'h1;
-	    end
-	    else begin
-	      timer_inc     = 1'h1;
-	      prescaler_rst = 1'h1;
-	      core_ctrl_new = CTRL_PRESCALER;
-	      core_ctrl_we  = 1'h1;
-	    end
-	  end
-	end
-
         default: begin
         end
       endcase // case (core_ctrl_reg)
diff --git a/hw/application_fpga/core/timer/tb/tb_timer_core.v b/hw/application_fpga/core/timer/tb/tb_timer_core.v
index 12c99d9..fe2df9d 100644
--- a/hw/application_fpga/core/timer/tb/tb_timer_core.v
+++ b/hw/application_fpga/core/timer/tb/tb_timer_core.v
@@ -144,6 +144,26 @@ module tb_timer_core();
   endtask // reset_dut
 
 
+  //----------------------------------------------------------------
+  // display_test_result()
+  //
+  // Display the accumulated test results.
+  //----------------------------------------------------------------
+  task display_test_result;
+    begin
+      if (error_ctr == 0)
+        begin
+          $display("--- All %02d test cases completed successfully", tc_ctr);
+        end
+      else
+        begin
+          $display("--- %02d tests completed - %02d test cases did not complete successfully.",
+                   tc_ctr, error_ctr);
+        end
+    end
+  endtask // display_test_result
+
+
   //----------------------------------------------------------------
   // wait_done()
   //
@@ -197,22 +217,42 @@ module tb_timer_core();
   // test1()
   //----------------------------------------------------------------
   task test1;
-    begin
-      tc_ctr = tc_ctr + 1;
-      tb_monitor = 1;
+    begin : test1
+      reg [31 : 0] test1_cycle_ctr_start;
+      reg [31 : 0] test1_counted_num_cycles;
+      reg [31 : 0] test1_expected_num_cycles;
 
-      $display("--- test1 started.");
-      dump_dut_state();
+      tc_ctr = tc_ctr + 1;
+
+      $display("--- test1: Run timer to set value started.");
+      $display("--- test1: prescaler: 6, timer: 9. Should take 6*9 + 1 = 55 cycles..");
       tb_prescaler_init = 32'h6;
       tb_timer_init     = 32'h9;
+      test1_expected_num_cycles = tb_prescaler_init * tb_timer_init + 1;
+
       #(CLK_PERIOD);
       tb_start = 1'h1;
+      test1_cycle_ctr_start = cycle_ctr;
       #(CLK_PERIOD);
       tb_start = 1'h0;
-      wait_done();
       #(CLK_PERIOD);
-      tb_monitor = 0;
-      $display("--- test1 completed.");
+
+      while (tb_running) begin
+	#(CLK_PERIOD);
+      end
+      test1_counted_num_cycles = cycle_ctr - test1_cycle_ctr_start;
+
+
+      if (test1_counted_num_cycles == test1_expected_num_cycles) begin
+	$display("--- test1: Corrcet number of cycles counted: %0d", test1_counted_num_cycles);
+      end
+      else begin
+	$display("--- test1: Error, expected %0d cycles, counted cycles: %0d",
+		 test1_expected_num_cycles, test1_counted_num_cycles);
+	error_ctr = error_ctr + 1;
+      end
+
+      $display("--- test1: Completed.");
       $display("");
     end
   endtask // test1
@@ -233,9 +273,10 @@ module tb_timer_core();
 
       test1();
 
+      display_test_result();
       $display("");
       $display("--- Simulation of timer core completed.");
-      $finish;
+      $finish(error_ctr);
     end // timer_core_test
 endmodule // tb_timer_core