From ddd969870ec938fe1a38fbc1c37232f61bc3c2c9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Tue, 18 Oct 2022 11:06:40 +0200 Subject: [PATCH] Count from init values to one, not zero --- hw/application_fpga/core/timer/rtl/timer_core.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/application_fpga/core/timer/rtl/timer_core.v b/hw/application_fpga/core/timer/rtl/timer_core.v index 224adb3..2c5104d 100644 --- a/hw/application_fpga/core/timer/rtl/timer_core.v +++ b/hw/application_fpga/core/timer/rtl/timer_core.v @@ -178,7 +178,7 @@ module timer_core( end else begin - if (prescaler_reg == 0) begin + if (prescaler_reg == 1) begin core_ctrl_new = CTRL_TIMER; core_ctrl_we = 1'h1; end else begin @@ -197,7 +197,7 @@ module timer_core( end else begin - if (timer_reg == 0) begin + if (timer_reg == 1) begin ready_new = 1'h1; ready_we = 1'h1; core_ctrl_new = CTRL_IDLE;