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fpga: Introduce CTS signals for UART

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Add incoming and outgoing CTS (Clear To Send) signals for the FPGA to
let the CH552 and FPGA signal each other that it is OK to send UART
data. The CTS signals indicate "OK to send" if high. If an incoming
CTS signal goes low, the receiver of that signal should immediatly
stop sending UART data.
This commit is contained in:
Jonas Thörnblad 2024-12-17 17:18:45 +01:00 • committed by Michael Cardell Widerkrantz
parent 6e062e7c89
commit dd4e970446
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GPG key ID: D3DB3DDF57E704E5
7 changed files with 54 additions and 5 deletions
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6
hw/application_fpga/tb/application_fpga_sim.v
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@ -33,6 +33,9 @@ module application_fpga_sim (
output wire interface_rx,
input wire interface_tx,
input wire interface_ch552_cts,
output wire interface_fpga_cts,
output wire spi_ss,
output wire spi_sck,
output wire spi_mosi,
@ -304,6 +307,9 @@ module application_fpga_sim (
.rxd(interface_tx),
.txd(interface_rx),
.ch552_cts(interface_ch552_cts),
.fpga_cts(interface_fpga_cts),
.cs(uart_cs),
.we(uart_we),
.address(uart_address),