fpga: Introduce CTS signals for UART

Add incoming and outgoing CTS (Clear To Send) signals for the FPGA to
let the CH552 and FPGA signal each other that it is OK to send UART
data. The CTS signals indicate "OK to send" if high. If an incoming
CTS signal goes low, the receiver of that signal should immediatly
stop sending UART data.

hw/application_fpga/core/uart/rtl/uart.v

@@ -55,6 +55,9 @@ module uart (
     input  wire rxd,
     output wire txd,
 
+    input  wire ch552_cts,
+    output wire fpga_cts,
+
     input  wire          cs,
     input  wire          we,
     input  wire [ 7 : 0] address,
@@ -110,6 +113,7 @@ module uart (
   reg  [31 : 0] tmp_read_data;
   reg           tmp_ready;
 
+  reg  [ 1 : 0] ch552_cts_reg;
 
   //----------------------------------------------------------------
   // Concurrent connectivity for ports etc.
@@ -158,9 +162,24 @@ module uart (
 
       .out_syn (fifo_out_syn),
       .out_data(fifo_out_data),
-      .out_ack (fifo_out_ack)
+      .out_ack (fifo_out_ack),
+
+      .fpga_cts(fpga_cts)
   );
 
+  //----------------------------------------------------------------
+  // reg_update
+  //----------------------------------------------------------------
+  always @(posedge clk) begin : reg_update
+    if (!reset_n) begin
+      ch552_cts_reg <= 2'h0;
+    end
+    else begin
+      ch552_cts_reg[0] <= ch552_cts;
+      ch552_cts_reg[1] <= ch552_cts_reg[0];
+    end
+  end  // reg_update
+
   //----------------------------------------------------------------
   // api
   //
@@ -208,7 +227,7 @@ module uart (
           end
 
           ADDR_TX_STATUS: begin
-            tmp_read_data = {31'h0, core_txd_ready};
+            tmp_read_data = {31'h0, core_txd_ready & ch552_cts_reg[1]};
           end
 
           default: begin

hw/application_fpga/core/uart/rtl/uart_fifo.v

@@ -48,7 +48,9 @@ module uart_fifo (
 
     output wire         out_syn,
     output wire [7 : 0] out_data,
-    input  wire         out_ack
+    input  wire         out_ack,
+
+    output wire         fpga_cts
 );
 
 
@@ -75,6 +77,7 @@ module uart_fifo (
   reg         in_ack_reg;
   reg         in_ack_new;
 
+  reg         fpga_cts_reg;
 
   //----------------------------------------------------------------
   // Wires
@@ -90,6 +93,7 @@ module uart_fifo (
   assign out_syn    = ~fifo_empty;
   assign out_data   = fifo_mem[out_ptr_reg];
   assign fifo_bytes = byte_ctr_reg;
+  assign fpga_cts   = fpga_cts_reg;
 
 
   //----------------------------------------------------------------
@@ -101,6 +105,7 @@ module uart_fifo (
       out_ptr_reg  <= 9'h0;
       byte_ctr_reg <= 9'h0;
       in_ack_reg   <= 1'h0;
+      fpga_cts_reg <= 1'h1;
     end
     else begin
       in_ack_reg <= in_ack_new;
@@ -120,6 +125,14 @@ module uart_fifo (
       if (byte_ctr_we) begin
         byte_ctr_reg <= byte_ctr_new;
       end
+
+      if (byte_ctr_reg >= 9'd486) begin  // FIFO is filled to ~95% or more
+        fpga_cts_reg <= 0;  // Signal to not send more data
+      end
+      else begin
+        fpga_cts_reg <= 1;  // Signal to send more data
+      end
+
     end
   end  // reg_update