Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2024-10-01 01:45:38 -04:00
Code Issues Packages Projects Releases Wiki Activity

FPGA: Ignore combinational loops that we want

Browse Source 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2024-06-17 13:53:16 +02:00 committed by dehanj
parent 49e81be1e1
commit d502b59062
No known key found for this signature in database
GPG Key ID: 3707A9DBF4BB8F1A
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/application_fpga/Makefile
View File

@ -189,7 +189,7 @@ LINT=verilator
# For Verilator 5.019 -Wno-GENUNNAMED needs to be added to LINT_FLAGS for the
# cell library.
LINT_FLAGS = +1364-2005ext+ --lint-only \
-Wall -Wno-DECLFILENAME -Wno-WIDTHEXPAND \
-Wall -Wno-DECLFILENAME -Wno-WIDTHEXPAND -Wno-UNOPTFLAT \
--timescale 1ns/1ns -DNO_ICE40_DEFAULT_ASSIGNMENTS
lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS)