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FPGA: Ignore combinational loops that we want

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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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Joachim Strömbergson 2024-06-17 13:53:16 +02:00 • committed by dehanj
parent 49e81be1e1
commit d502b59062
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hw/application_fpga/Makefile
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@ -189,7 +189,7 @@ LINT=verilator
# For Verilator 5.019 -Wno-GENUNNAMED needs to be added to LINT_FLAGS for the # For Verilator 5.019 -Wno-GENUNNAMED needs to be added to LINT_FLAGS for the
# cell library. # cell library.
LINT_FLAGS = +1364-2005ext+ --lint-only \ LINT_FLAGS = +1364-2005ext+ --lint-only \
-Wall -Wno-DECLFILENAME -Wno-WIDTHEXPAND \ -Wall -Wno-DECLFILENAME -Wno-WIDTHEXPAND -Wno-UNOPTFLAT \
--timescale 1ns/1ns -DNO_ICE40_DEFAULT_ASSIGNMENTS --timescale 1ns/1ns -DNO_ICE40_DEFAULT_ASSIGNMENTS
lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS) lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS)