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Explicity make uart_core.rx_data a wire (#140)

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blaufish 2023-08-16 10:43:04 +02:00 committed by GitHub
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commit cced6aec31
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hw/application_fpga/core/uart/rtl/uart_core.v
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@ -61,7 +61,7 @@ module uart_core(
// Internal receive interface.
output wire rxd_syn,
output [7 : 0] rxd_data,
output wire [7 : 0] rxd_data,
input wire rxd_ack,
// Internal transmit interface.