fpga: Experimental fpga build for uwg30 package

nextpnr-ice40 fails with:

```
Info: Placing PLLs..
ERROR: PLL 'reset_gen_inst.pll_inst' couldn't be placed anywhere, no
suitable BEL found.
    PLL bel 'X12/Y31/pll_3' cannot be used as it conflicts with input
'interface_ch552_cts$sb_io' on pin 'B3'.
```

hw/application_fpga/Makefile

@@ -34,7 +34,8 @@ TARGET_FREQ ?= 24
 # bits wide; an EBR is 128 32-bits words)
 BRAM_FW_SIZE ?= 2048
 
-PIN_FILE ?= application_fpga_tk1.pcf
+PIN_FILE ?= application_fpga_tk1_uwg30.pcf
+FPGA_PACKAGE ?= uwg30
 
 SIZE ?= llvm-size
 OBJCOPY ?= llvm-objcopy
@@ -399,7 +400,7 @@ application_fpga_par.json: synth.json $(P)/data/$(PIN_FILE)
 		--freq $(TARGET_FREQ) \
 		--ignore-loops \
 		--up5k \
-		--package sg48 \
+		--package $(FPGA_PACKAGE) \
 		--json $< \
 		--pcf $(P)/data/$(PIN_FILE) \
 		--write $@ \
@@ -412,7 +413,7 @@ application_fpga.asc: application_fpga_par.json $(P)/data/uds.hex $(P)/data/udi.
 	OUT_ASC=$@ \
 	$(NEXTPNR_PATH)nextpnr-ice40 \
 		--up5k \
-		--package sg48 \
+		--package $(FPGA_PACKAGE) \
 		--ignore-loops \
 		--json $< \
 		--run tools/patch_uds_udi.py
@@ -489,7 +490,7 @@ check-hardware:
 # Post build analysis.
 #-------------------------------------------------------------------
 timing: application_fpga.asc $(P)/data/$(PIN_FILE)
-	$(ICESTORM_PATH)icetime -c 18 -tmd up5k -P sg48 -p $(P)/data/$(PIN_FILE) -t $<
+	$(ICESTORM_PATH)icetime -c 18 -tmd up5k -P $(FPGA_PACKAGE) -p $(P)/data/$(PIN_FILE) -t $<
 
 view: tb_application_fpga_vcd
 	gtkwave $< application_fpga.gtkw

hw/application_fpga/core/tk1/rtl/tk1.v

@@ -211,9 +211,9 @@ module tk1 #(
       .RGB1(led_g),
       .RGB2(led_b),
       .RGBLEDEN(1'h1),
-      .RGB0PWM(muxed_led[LED_R_BIT]),
+      .RGB0PWM(muxed_led[LED_B_BIT]),
       .RGB1PWM(muxed_led[LED_G_BIT]),
-      .RGB2PWM(muxed_led[LED_B_BIT]),
+      .RGB2PWM(muxed_led[LED_R_BIT]),
       .CURREN(1'b1)
   );
   /* verilator lint_on PINMISSING */

hw/application_fpga/data/application_fpga_tk1_uwg30.pcf

@@ -0,0 +1,47 @@
+#=======================================================================
+#
+# application_fpga_tk1_uwg30.pcf
+# ------------------------------
+# Pin constraints file for the Application FPGA design to be used
+# on the tk1 board with the CH552 MCU used as a USB-serial chip.
+# This version targets the UWG30 package.
+#
+#
+# Copyright (C) 2022 - Tillitis AB
+# SPDX-License-Identifier: GPL-2.0-only
+#
+#=======================================================================
+
+# UART.
+set_io interface_rx A2
+set_io interface_tx A1
+set_io interface_ch552_cts B3
+set_io interface_fpga_cts A4
+
+
+# SPI master to flash memory.
+set_io spi_miso E1
+set_io spi_sck  D1
+set_io spi_ss   C1
+set_io spi_mosi F1
+
+
+# Touch sense.
+set_io touch_event B1
+
+
+# GPIOs.
+#set_io app_gpio1 36
+#set_io app_gpio2 38
+#set_io app_gpio3 45
+#set_io app_gpio4 46
+
+
+# LEDs
+set_io led_r A5
+set_io led_b B5
+set_io led_g C5
+
+#=======================================================================
+# EOF application_fpga_tk1_uwg30.pcf
+#=======================================================================

hw/application_fpga/rtl/application_fpga.v

@@ -30,10 +30,10 @@ module application_fpga (
 
     input wire touch_event,
 
-    input  wire app_gpio1,
+    // input  wire app_gpio1,
-    input  wire app_gpio2,
+    // input  wire app_gpio2,
-    output wire app_gpio3,
+    // output wire app_gpio3,
-    output wire app_gpio4,
+    // output wire app_gpio4,
 
     output wire led_r,
     output wire led_g,
@@ -364,10 +364,10 @@ module application_fpga (
       .led_g(led_g),
       .led_b(led_b),
 
-      .gpio1(app_gpio1),
+      .gpio1(),
-      .gpio2(app_gpio2),
+      .gpio2(),
-      .gpio3(app_gpio3),
+      .gpio3(),
-      .gpio4(app_gpio4),
+      .gpio4(),
 
       .syscall(irq31_eoi),
 

hw/application_fpga/tb/application_fpga_sim.v

@@ -43,10 +43,10 @@ module application_fpga_sim (
 
     input wire touch_event,
 
-    input  wire app_gpio1,
+    // input  wire app_gpio1,
-    input  wire app_gpio2,
+    // input  wire app_gpio2,
-    output wire app_gpio3,
+    // output wire app_gpio3,
-    output wire app_gpio4,
+    // output wire app_gpio4,
 
     output wire led_r,
     output wire led_g,
@@ -377,10 +377,10 @@ module application_fpga_sim (
       .led_g(led_g),
       .led_b(led_b),
 
-      .gpio1(app_gpio1),
+      .gpio1(),
-      .gpio2(app_gpio2),
+      .gpio2(),
-      .gpio3(app_gpio3),
+      .gpio3(),
-      .gpio4(app_gpio4),
+      .gpio4(),
 
       .syscall(irq31_eoi),