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fpga: Experimental fpga build for uwg30 package

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nextpnr-ice40 fails with:

```
Info: Placing PLLs..
ERROR: PLL 'reset_gen_inst.pll_inst' couldn't be placed anywhere, no
suitable BEL found.
    PLL bel 'X12/Y31/pll_3' cannot be used as it conflicts with input
'interface_ch552_cts$sb_io' on pin 'B3'.
```
This commit is contained in:
Mikael Ågren 2025-05-09 14:22:14 +02:00
parent daa7807c0f
commit c98249c3e3
No known key found for this signature in database
GPG key ID: E02DA3D397792C46
5 changed files with 70 additions and 22 deletions
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47
hw/application_fpga/data/application_fpga_tk1_uwg30.pcf Normal file
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#=======================================================================
#
# application_fpga_tk1_uwg30.pcf
# ------------------------------
# Pin constraints file for the Application FPGA design to be used
# on the tk1 board with the CH552 MCU used as a USB-serial chip.
# This version targets the UWG30 package.
#
#
# Copyright (C) 2022 - Tillitis AB
# SPDX-License-Identifier: GPL-2.0-only
#
#=======================================================================
# UART.
set_io interface_rx A2
set_io interface_tx A1
set_io interface_ch552_cts B3
set_io interface_fpga_cts A4
# SPI master to flash memory.
set_io spi_miso E1
set_io spi_sck D1
set_io spi_ss C1
set_io spi_mosi F1
# Touch sense.
set_io touch_event B1
# GPIOs.
#set_io app_gpio1 36
#set_io app_gpio2 38
#set_io app_gpio3 45
#set_io app_gpio4 46
# LEDs
set_io led_r A5
set_io led_b B5
set_io led_g C5
#=======================================================================
# EOF application_fpga_tk1_uwg30.pcf
#=======================================================================