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fpga: Experimental fpga build for uwg30 package
nextpnr-ice40 fails with:
```
Info: Placing PLLs..
ERROR: PLL 'reset_gen_inst.pll_inst' couldn't be placed anywhere, no
suitable BEL found.
PLL bel 'X12/Y31/pll_3' cannot be used as it conflicts with input
'interface_ch552_cts$sb_io' on pin 'B3'.
```
This commit is contained in:
Mikael Ågren
parent
daa7807c0f
commit
c98249c3e3
5 changed files with 70 additions and 22 deletions
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@ -34,7 +34,8 @@ TARGET_FREQ ?= 24
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# bits wide; an EBR is 128 32-bits words)
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BRAM_FW_SIZE ?= 2048
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PIN_FILE ?= application_fpga_tk1.pcf
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PIN_FILE ?= application_fpga_tk1_uwg30.pcf
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FPGA_PACKAGE ?= uwg30
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SIZE ?= llvm-size
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OBJCOPY ?= llvm-objcopy
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@ -399,7 +400,7 @@ application_fpga_par.json: synth.json $(P)/data/$(PIN_FILE)
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--freq $(TARGET_FREQ) \
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--ignore-loops \
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--up5k \
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--package sg48 \
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--package $(FPGA_PACKAGE) \
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--json $< \
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--pcf $(P)/data/$(PIN_FILE) \
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--write $@ \
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@ -412,7 +413,7 @@ application_fpga.asc: application_fpga_par.json $(P)/data/uds.hex $(P)/data/udi.
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OUT_ASC=$@ \
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$(NEXTPNR_PATH)nextpnr-ice40 \
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--up5k \
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--package sg48 \
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--package $(FPGA_PACKAGE) \
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--ignore-loops \
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--json $< \
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--run tools/patch_uds_udi.py
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@ -489,7 +490,7 @@ check-hardware:
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# Post build analysis.
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#-------------------------------------------------------------------
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timing: application_fpga.asc $(P)/data/$(PIN_FILE)
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$(ICESTORM_PATH)icetime -c 18 -tmd up5k -P sg48 -p $(P)/data/$(PIN_FILE) -t $<
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$(ICESTORM_PATH)icetime -c 18 -tmd up5k -P $(FPGA_PACKAGE) -p $(P)/data/$(PIN_FILE) -t $<
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view: tb_application_fpga_vcd
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gtkwave $< application_fpga.gtkw
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@ -211,9 +211,9 @@ module tk1 #(
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.RGB1(led_g),
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.RGB2(led_b),
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.RGBLEDEN(1'h1),
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.RGB0PWM(muxed_led[LED_R_BIT]),
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.RGB0PWM(muxed_led[LED_B_BIT]),
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.RGB1PWM(muxed_led[LED_G_BIT]),
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.RGB2PWM(muxed_led[LED_B_BIT]),
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.RGB2PWM(muxed_led[LED_R_BIT]),
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.CURREN(1'b1)
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);
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/* verilator lint_on PINMISSING */
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47
hw/application_fpga/data/application_fpga_tk1_uwg30.pcf
Normal file
47
hw/application_fpga/data/application_fpga_tk1_uwg30.pcf
Normal file
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@ -0,0 +1,47 @@
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#=======================================================================
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#
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# application_fpga_tk1_uwg30.pcf
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# ------------------------------
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# Pin constraints file for the Application FPGA design to be used
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# on the tk1 board with the CH552 MCU used as a USB-serial chip.
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# This version targets the UWG30 package.
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#
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#
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# Copyright (C) 2022 - Tillitis AB
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# SPDX-License-Identifier: GPL-2.0-only
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#
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#=======================================================================
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# UART.
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set_io interface_rx A2
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set_io interface_tx A1
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set_io interface_ch552_cts B3
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set_io interface_fpga_cts A4
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# SPI master to flash memory.
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set_io spi_miso E1
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set_io spi_sck D1
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set_io spi_ss C1
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set_io spi_mosi F1
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# Touch sense.
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set_io touch_event B1
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# GPIOs.
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#set_io app_gpio1 36
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#set_io app_gpio2 38
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#set_io app_gpio3 45
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#set_io app_gpio4 46
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# LEDs
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set_io led_r A5
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set_io led_b B5
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set_io led_g C5
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#=======================================================================
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# EOF application_fpga_tk1_uwg30.pcf
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#=======================================================================
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@ -30,10 +30,10 @@ module application_fpga (
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input wire touch_event,
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input wire app_gpio1,
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input wire app_gpio2,
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output wire app_gpio3,
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output wire app_gpio4,
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// input wire app_gpio1,
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// input wire app_gpio2,
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// output wire app_gpio3,
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// output wire app_gpio4,
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output wire led_r,
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output wire led_g,
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@ -364,10 +364,10 @@ module application_fpga (
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.led_g(led_g),
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.led_b(led_b),
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.gpio1(app_gpio1),
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.gpio2(app_gpio2),
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.gpio3(app_gpio3),
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.gpio4(app_gpio4),
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.gpio1(),
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.gpio2(),
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.gpio3(),
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.gpio4(),
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.syscall(irq31_eoi),
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@ -43,10 +43,10 @@ module application_fpga_sim (
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input wire touch_event,
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input wire app_gpio1,
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input wire app_gpio2,
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output wire app_gpio3,
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output wire app_gpio4,
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// input wire app_gpio1,
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// input wire app_gpio2,
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// output wire app_gpio3,
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// output wire app_gpio4,
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output wire led_r,
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output wire led_g,
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@ -377,10 +377,10 @@ module application_fpga_sim (
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.led_g(led_g),
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.led_b(led_b),
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.gpio1(app_gpio1),
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.gpio2(app_gpio2),
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.gpio3(app_gpio3),
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.gpio4(app_gpio4),
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.gpio1(),
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.gpio2(),
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.gpio3(),
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.gpio4(),
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.syscall(irq31_eoi),
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