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Config verilator lint to ignore known 3rd-party warnings; let warnings be fatal

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Signed-off-by: Daniel Lublin <daniel@lublin.se>
This commit is contained in:
Daniel Lublin 2023-02-28 09:12:19 +01:00
parent 4995fdb93d
commit c9593f11c8
3 changed files with 11 additions and 4 deletions
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1
.github/workflows/ci.yaml vendored
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@ -44,7 +44,6 @@ jobs:
make -C fw/tk1 checkfmt make -C fw/tk1 checkfmt
make -C fw/testfw checkfmt make -C fw/testfw checkfmt
# this should to fail on errors, but not on warnings (using -Wno-fatal)
- name: lint verilog using verilator - name: lint verilog using verilator
working-directory: hw/application_fpga working-directory: hw/application_fpga
run: make lint run: make lint

10
hw/application_fpga/Makefile
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@ -6,7 +6,7 @@
# HW targets as well as its firmware. # HW targets as well as its firmware.
# #
# #
# Copyright (C) 2022 - Tillitis AB # Copyright (C) 2022, 2023 - Tillitis AB
# SPDX-License-Identifier: GPL-2.0-only # SPDX-License-Identifier: GPL-2.0-only
# #
#======================================================================= #=======================================================================
@ -147,7 +147,7 @@ testfw.hex: testfw.bin testfw_size_mismatch
# Source linting. # Source linting.
#------------------------------------------------------------------- #-------------------------------------------------------------------
LINT=verilator LINT=verilator
LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME \ LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-DECLFILENAME \
--timescale 1ns/1ns -DNO_ICE40_DEFAULT_ASSIGNMENTS --timescale 1ns/1ns -DNO_ICE40_DEFAULT_ASSIGNMENTS
lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS) lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS)
@ -156,7 +156,11 @@ lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS)
-DFIRMWARE_HEX=\"$(P)/firmware.hex\" \ -DFIRMWARE_HEX=\"$(P)/firmware.hex\" \
-DUDS_HEX=\"$(P)/data/uds.hex\" \ -DUDS_HEX=\"$(P)/data/uds.hex\" \
-DUDI_HEX=\"$(P)/data/udi.hex\" \ -DUDI_HEX=\"$(P)/data/udi.hex\" \
--top-module application_fpga $^ &> lint_issues.txt --top-module application_fpga \
config.vlt $^ \
>lint_issues.txt 2>&1 \
&& { rm -f lint_issues.txt; exit 0; } \
|| { cat lint_issues.txt; exit 1; }
.PHONY: lint .PHONY: lint

4
hw/application_fpga/config.vlt Normal file
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@ -0,0 +1,4 @@
`verilator_config
lint_off -rule UNUSED -file "*/ice40/cells_sim.v"
lint_off -rule UNDRIVEN -file "*/ice40/cells_sim.v"
lint_off -rule BLKSEQ -file "*/picorv32.v"