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Change filename personalize.py to patch_uds_udi.py
Also adding a more detailed explaination of what the script intends to do
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@ -248,7 +248,7 @@ application_fpga_par.json: synth.json $(P)/data/$(PIN_FILE)
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--pcf $(P)/data/$(PIN_FILE) --write $@
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application_fpga.asc: application_fpga_par.json $(P)/data/uds.hex $(P)/data/udi.hex
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UDS_HEX="$(P)/data/uds.hex" UDI_HEX="$(P)/data/udi.hex" OUT_ASC=$@ $(NEXTPNR_PATH)nextpnr-ice40 --up5k --package sg48 --ignore-loops --json $< --run tools/personalize.py
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UDS_HEX="$(P)/data/uds.hex" UDI_HEX="$(P)/data/udi.hex" OUT_ASC=$@ $(NEXTPNR_PATH)nextpnr-ice40 --up5k --package sg48 --ignore-loops --json $< --run tools/patch_uds_udi.py
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application_fpga.bin: application_fpga.asc bram_fw.hex firmware.hex
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$(ICESTORM_PATH)icebram -v bram_fw.hex firmware.hex < $< > $<.tmp
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@ -1,17 +1,34 @@
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# -*- coding: utf-8 -*-
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#=======================================================================
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#
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# personalize.py
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# Copyright (C) 2023 Tillitis AB
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# Written by Myrtle Shah <gatecat@ds0.me>
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# SPDX-License-Identifier: GPL-2.0-only
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#
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# patch_uds_udi.py
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# --------------
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# Python program that patches the UDS and UDI implemented using
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# named LUT4 instances to have unique initial values, not the generic
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# values used during synthesis, p&r and mapping. This allows us to
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# generate device unique bitstreams without running the complete flow.
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#
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# Both the UDI and UDS are using bit indexing from 32 LUTs for each
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# word, i.e., the first word consists of bit 0 from each 32 LUTs and
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# so on.
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#
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# The size requirements for the UDI and UDS are specified as 1 bit (8
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# bytes of data) and 3 bits (32 bytes of data), respectively. The UDI
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# does not occupy the entire LUT4 instance, and to conserve resources,
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# the pattern of the UDI is repeated over the unused portion of the
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# LUT4 instance. This eliminates the need to drive the three MSB pins
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# while still achieving the correct output.
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#
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# In the case of UDS, a read-enable signal is present, and the most
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# significant bit serves as the read-enable input. This requires the
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# lower half of initialization bits to be forced to zero, ensuring
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# that the memory outputs zero when the read-enable signal is
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# inactive.
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#
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# Copyright (C) 2023 Tillitis AB
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# Written by Myrtle Shah <gatecat@ds0.me>
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# SPDX-License-Identifier: GPL-2.0-only
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#
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#=======================================================================
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