From c5ddfce135673bd2820c19be0a79dc1dd290a3ec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Thu, 15 Aug 2024 12:21:37 +0200 Subject: [PATCH] (fpga) Fix reset, add self checking test case. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reset the free_running_reg to reset Make test1 self checking. Signed-off-by: Joachim StroĢˆmbergson --- hw/application_fpga/core/timer/rtl/timer.v | 11 ++++---- hw/application_fpga/core/timer/tb/tb_timer.v | 29 +++++++++++++------- 2 files changed, 25 insertions(+), 15 deletions(-) diff --git a/hw/application_fpga/core/timer/rtl/timer.v b/hw/application_fpga/core/timer/rtl/timer.v index 27216f1..1ddbeb4 100644 --- a/hw/application_fpga/core/timer/rtl/timer.v +++ b/hw/application_fpga/core/timer/rtl/timer.v @@ -103,10 +103,11 @@ module timer( always @ (posedge clk) begin : reg_update if (!reset_n) begin - start_reg <= 1'h0; - stop_reg <= 1'h0; - prescaler_reg <= 32'h0; - timer_reg <= 32'h0; + start_reg <= 1'h0; + stop_reg <= 1'h0; + free_running_reg <= 1'h0; + prescaler_reg <= 32'h0; + timer_reg <= 32'h0; end else begin start_reg <= start_new; @@ -121,7 +122,7 @@ module timer( end if (free_running_we) begin - free_running_reg <= write_data[0]; + free_running_reg <= write_data[FREE_RUNNING_BIT]; end end end // reg_update diff --git a/hw/application_fpga/core/timer/tb/tb_timer.v b/hw/application_fpga/core/timer/tb/tb_timer.v index 39c7a10..7a0e2ea 100644 --- a/hw/application_fpga/core/timer/tb/tb_timer.v +++ b/hw/application_fpga/core/timer/tb/tb_timer.v @@ -250,6 +250,7 @@ module tb_timer(); //---------------------------------------------------------------- // test1() + // Set timer and scaler and then start the timer. Wait // for the ready flag to be asserted again. //---------------------------------------------------------------- @@ -257,6 +258,8 @@ module tb_timer(); begin : test1 reg [31 : 0] time_start; reg [31 : 0] time_stop; + reg [31 : 0] time_expected; + reg [31 : 0] time_counted; tc_ctr = tc_ctr + 1; tb_monitor = 0; @@ -264,24 +267,30 @@ module tb_timer(); $display(""); $display("--- test1: started."); - write_word(ADDR_PRESCALER, 8'h02); - write_word(ADDR_TIMER, 8'h10); + write_word(ADDR_PRESCALER, 32'h6); + write_word(ADDR_TIMER, 32'h9); + time_expected = 32'h6 * 32'h9; + write_word(ADDR_CTRL, 32'h1); time_start = cycle_ctr; - write_word(ADDR_CTRL, 8'h01); - #(2 * CLK_PERIOD); + #(CLK_PERIOD); read_word(ADDR_STATUS); while (read_data) begin read_word(ADDR_STATUS); end - time_stop = cycle_ctr; - write_word(CTRL_START_BIT, 8'h02); + time_counted = time_stop - time_start; - $display("--- test1: Cycles between start and stop: %d", (time_stop - time_start)); - #(CLK_PERIOD); - tb_monitor = 0; + + if (time_counted == time_expected) begin + $display("--- test1: Correct number of cycles counted: %0d", time_counted); + end + else begin + $display("--- test1: Error, expected %0d cycles, counted cycles: %0d", + time_expected, time_counted); + error_ctr = error_ctr + 1; + end $display("--- test1: completed."); $display(""); @@ -308,7 +317,7 @@ module tb_timer(); $display(" -= Testbench for timer completed =-"); $display(" ==============================="); $display(""); - $finish; + $finish(error_ctr); end // timer_test endmodule // tb_timer