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FPGA: Remove redundant clock cycle counter

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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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Joachim Strömbergson 2024-06-19 13:50:13 +02:00 committed by dehanj
parent ec77b15eb8
commit c271b48a53
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GPG Key ID: 3707A9DBF4BB8F1A
1 changed files with 0 additions and 40 deletions
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hw/application_fpga/core/tk1/rtl/tk1_spi_master.v
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@ -50,8 +50,6 @@ module tk1_spi_master(
localparam CTRL_NEG_FLANK = 3'h2; localparam CTRL_NEG_FLANK = 3'h2;
localparam CTRL_NEXT = 3'h3; localparam CTRL_NEXT = 3'h3;
localparam SPI_CLK_CYCLES = 4'h1;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Registers including update variables and write enable. // Registers including update variables and write enable.
@ -74,10 +72,6 @@ module tk1_spi_master(
reg spi_miso_sample_reg; reg spi_miso_sample_reg;
reg [3 : 0] spi_clk_ctr_reg;
reg [3 : 0] spi_clk_ctr_new;
reg spi_clk_ctr_rst;
reg [2 : 0] spi_bit_ctr_reg; reg [2 : 0] spi_bit_ctr_reg;
reg [2 : 0] spi_bit_ctr_new; reg [2 : 0] spi_bit_ctr_new;
reg spi_bit_ctr_rst; reg spi_bit_ctr_rst;
@ -93,12 +87,6 @@ module tk1_spi_master(
reg spi_ctrl_we; reg spi_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg spi_clk_cycles_reached;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Concurrent connectivity for ports etc. // Concurrent connectivity for ports etc.
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -120,7 +108,6 @@ module tk1_spi_master(
spi_miso_sample_reg <= 1'h0; spi_miso_sample_reg <= 1'h0;
spi_tx_data_reg <= 8'h0; spi_tx_data_reg <= 8'h0;
spi_rx_data_reg <= 8'h0; spi_rx_data_reg <= 8'h0;
spi_clk_ctr_reg <= 4'h0;
spi_bit_ctr_reg <= 3'h0; spi_bit_ctr_reg <= 3'h0;
spi_ready_reg <= 1'h1; spi_ready_reg <= 1'h1;
spi_ctrl_reg <= CTRL_IDLE; spi_ctrl_reg <= CTRL_IDLE;
@ -128,7 +115,6 @@ module tk1_spi_master(
else begin else begin
spi_miso_sample_reg <= spi_miso; spi_miso_sample_reg <= spi_miso;
spi_clk_ctr_reg <= spi_clk_ctr_new;
if (spi_enable_vld) begin if (spi_enable_vld) begin
spi_ss_reg <= ~spi_enable; spi_ss_reg <= ~spi_enable;
@ -161,31 +147,6 @@ module tk1_spi_master(
end // reg_update end // reg_update
//----------------------------------------------------------------
// cpi_clk_ctr
//
// Resettable clock cycle counter used to generate the SPI clock.
//----------------------------------------------------------------
always @*
begin : spi_clk_ctr
spi_clk_cycles_reached = 1'h0;
if (spi_clk_ctr_reg == SPI_CLK_CYCLES) begin
spi_clk_cycles_reached = 1'h1;
end
else begin
spi_clk_cycles_reached = 1'h0;
end
if (spi_clk_ctr_rst) begin
spi_clk_ctr_new = 4'h0;
end
else begin
spi_clk_ctr_new = spi_clk_ctr_reg + 1'h1;
end
end
//---------------------------------------------------------------- //----------------------------------------------------------------
// bit_ctr // bit_ctr
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -259,7 +220,6 @@ module tk1_spi_master(
begin : spi_master_ctrl begin : spi_master_ctrl
spi_rx_data_nxt = 1'h0; spi_rx_data_nxt = 1'h0;
spi_tx_data_nxt = 1'h0; spi_tx_data_nxt = 1'h0;
spi_clk_ctr_rst = 1'h0;
spi_csk_new = 1'h0; spi_csk_new = 1'h0;
spi_csk_we = 1'h0; spi_csk_we = 1'h0;
spi_bit_ctr_rst = 1'h0; spi_bit_ctr_rst = 1'h0;