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Fix Verilator sim by adding separate reset generator

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Joachim Strömbergson 2022-10-03 12:55:24 +02:00
parent 1aa2d7bd95
commit b2ca3f2ea0
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GPG Key ID: 865B8A548EA61679
2 changed files with 82 additions and 7 deletions
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17
hw/application_fpga/Makefile
View File

@ -42,13 +42,16 @@ ASFLAGS = -target riscv32-unknown-none-elf -march=rv32imc -mabi=ilp32 -mno-relax
ICE40_SIM_CELLS = $(shell yosys-config --datdir/ice40/cells_sim.v) ICE40_SIM_CELLS = $(shell yosys-config --datdir/ice40/cells_sim.v)
# FPGA source files. # FPGA specific Verilog source files.
TOP_SRC = $(P)/rtl/application_fpga.v FPGA_SRC = $(P)/rtl/application_fpga.v \
$(P)/rtl/clk_reset_gen.v
VERILATOR_TOP_SRC = $(P)/tb/application_fpga_vsim.v # Verilator simulation specific Verilog source files.
VERILATOR_FPGA_SRC = $(P)/tb/application_fpga_vsim.v \
$(P)/tb/reset_gen_vsim.v
# Common verilog source files.
VERILOG_SRCS = \ VERILOG_SRCS = \
$(P)/rtl/clk_reset_gen.v \
$(P)/rtl/ram.v \ $(P)/rtl/ram.v \
$(P)/rtl/rom.v \ $(P)/rtl/rom.v \
$(P)/core/picorv32/rtl/picorv32.v \ $(P)/core/picorv32/rtl/picorv32.v \
@ -137,7 +140,7 @@ LINT=verilator
LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME \ LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME \
--timescale 1ns/1ns -DNO_ICE40_DEFAULT_ASSIGNMENTS --timescale 1ns/1ns -DNO_ICE40_DEFAULT_ASSIGNMENTS
lint: $(TOP_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS) lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS)
$(LINT) $(LINT_FLAGS) \ $(LINT) $(LINT_FLAGS) \
-DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \ -DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
-DFIRMWARE_HEX=\"$(P)/firmware.hex\" \ -DFIRMWARE_HEX=\"$(P)/firmware.hex\" \
@ -150,7 +153,7 @@ lint: $(TOP_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS)
#------------------------------------------------------------------- #-------------------------------------------------------------------
# Build Verilator compiled simulation for the design. # Build Verilator compiled simulation for the design.
#------------------------------------------------------------------- #-------------------------------------------------------------------
verilator: $(VERILATOR_TOP_SRC) $(VERILOG_SRCS) firmware.hex $(ICE40_SIM_CELLS) \ verilator: $(VERILATOR_FPGA_SRC) $(VERILOG_SRCS) firmware.hex $(ICE40_SIM_CELLS) \
$(P)/tb/application_fpga_verilator.cc $(P)/tb/application_fpga_verilator.cc
verilator --timescale 1ns/1ns -DNO_ICE40_DEFAULT_ASSIGNMENTS \ verilator --timescale 1ns/1ns -DNO_ICE40_DEFAULT_ASSIGNMENTS \
-Wall -Wno-COMBDLY -Wno-lint \ -Wall -Wno-COMBDLY -Wno-lint \
@ -168,7 +171,7 @@ verilator: $(VERILATOR_TOP_SRC) $(VERILOG_SRCS) firmware.hex $(ICE40_SIM_CELLS)
# Main FPGA build flow. # Main FPGA build flow.
# Synthesis. Place & Route. Bitstream generation. # Synthesis. Place & Route. Bitstream generation.
#------------------------------------------------------------------- #-------------------------------------------------------------------
synth.json: $(TOP_SRC) $(VERILOG_SRCS) bram_fw.hex $(P)/data/uds.hex $(P)/data/udi.hex synth.json: $(FPGA_SRC) $(VERILOG_SRCS) bram_fw.hex $(P)/data/uds.hex $(P)/data/udi.hex
$(YOSYS_PATH)yosys -v3 -l synth.log -DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \ $(YOSYS_PATH)yosys -v3 -l synth.log -DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
-DFIRMWARE_HEX=\"$(P)/bram_fw.hex\" \ -DFIRMWARE_HEX=\"$(P)/bram_fw.hex\" \
-DUDS_HEX=\"$(P)/data/uds.hex\" \ -DUDS_HEX=\"$(P)/data/uds.hex\" \

72
hw/application_fpga/tb/reset_gen_vsim.v Normal file
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@ -0,0 +1,72 @@
//======================================================================
//
// reset_gen_vsim.v
// ----------------
// Reset generator Verilator simulation of the application_fpga.
//
//
// Author: Joachim Strombergson
// Copyright (C) 2022 - Tillitis AB
// SPDX-License-Identifier: GPL-2.0-only
//
//======================================================================
`default_nettype none
module reset_gen #(parameter RESET_CYCLES = 200)
(
input wire clk,
output wire rst_n
);
//----------------------------------------------------------------
// Registers with associated wires.
//----------------------------------------------------------------
reg [7 : 0] rst_ctr_reg = 8'h0;
reg [7 : 0] rst_ctr_new;
reg rst_ctr_we;
reg rst_n_reg = 1'h0;
reg rst_n_new;
//----------------------------------------------------------------
// Concurrent assignment.
//----------------------------------------------------------------
assign rst_n = rst_n_reg;
//----------------------------------------------------------------
// reg_update.
//----------------------------------------------------------------
always @(posedge clk)
begin : reg_update
rst_n_reg <= rst_n_new;
if (rst_ctr_we)
rst_ctr_reg <= rst_ctr_new;
end
//----------------------------------------------------------------
// rst_logic.
//----------------------------------------------------------------
always @*
begin : rst_logic
rst_n_new = 1'h1;
rst_ctr_new = 8'h0;
rst_ctr_we = 1'h0;
if (rst_ctr_reg < RESET_CYCLES) begin
rst_n_new = 1'h0;
rst_ctr_new = rst_ctr_reg + 1'h1;
rst_ctr_we = 1'h1;
end
end
endmodule // reset_gen
//======================================================================
// EOF reset_gen.v
//======================================================================