From aeafc244fb35fa4f692e1c71ddd32b889ba7c5b2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Tue, 29 Nov 2022 13:47:43 +0100 Subject: [PATCH] Add link to SW for API descriptions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Joachim Strömbergson --- doc/system_description/fpga.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/system_description/fpga.md b/doc/system_description/fpga.md index 7e3f528..3408b75 100644 --- a/doc/system_description/fpga.md +++ b/doc/system_description/fpga.md @@ -21,11 +21,11 @@ cores in different ways given the current exection mode. There are two execution modes - firmware and application. Basically, in application mode the access is more restrictive. -The API for all cores is described in XYZ. +The API for all cores is described in the [Software documentation](software.md). + ### Cores - #### CPU The CPU core is an instance of the [PicoRV32 core](https://github.com/YosysHQ/picorv32). The instance enables the following features