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Harmonize the naming of firmware and app mode.

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- The API changes name from `_SWITCH_APP` to `_SYSTEM_MODE_CTRL`.
- The registers and wires changes name to `system_mode_*`, instead of a
  mix of `switch_app_*` and `fw_app_mode`.
This commit is contained in:
Jonas Thörnblad 2024-10-28 15:25:28 +01:00 committed by Daniel Jobson
parent 69ef6dde8b
commit aea2e319eb
No known key found for this signature in database
GPG Key ID: 3707A9DBF4BB8F1A
16 changed files with 149 additions and 146 deletions
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4
doc/system_description/system_description.md
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@ -228,7 +228,7 @@ Assigned core prefixes:
`sw`. Exceptions are `UDS`, `FW_RAM` and `QEMU_DEBUG`. `sw`. Exceptions are `UDS`, `FW_RAM` and `QEMU_DEBUG`.
| *name* | *fw* | *app* | *size* | *type* | *content* | *description* | | *name* | *fw* | *app* | *size* | *type* | *content* | *description* |
|-------------------|-------|-----------|--------|----------|-----------|-------------------------------------------------------------------------| |--------------------|-------|-----------|--------|----------|-----------|-------------------------------------------------------------------------|
| `TRNG_STATUS` | r | r | | | | TRNG_STATUS_READY_BIT is 1 when an entropy word is available. | | `TRNG_STATUS` | r | r | | | | TRNG_STATUS_READY_BIT is 1 when an entropy word is available. |
| `TRNG_ENTROPY` | r | r | 4B | u32 | | Entropy word. Reading a word will clear status. | | `TRNG_ENTROPY` | r | r | 4B | u32 | | Entropy word. Reading a word will clear status. |
| `TIMER_CTRL` | r/w | r/w | | | | If TIMER_STATUS_RUNNING_BIT in TIMER_STATUS is 0, setting | | `TIMER_CTRL` | r/w | r/w | | | | If TIMER_STATUS_RUNNING_BIT in TIMER_STATUS is 0, setting |
@ -256,7 +256,7 @@ Assigned core prefixes:
| `NAME0` | r | r | 4B | char[4] | "tk1 " | ID of core/stick | | `NAME0` | r | r | 4B | char[4] | "tk1 " | ID of core/stick |
| `NAME1` | r | r | 4B | char[4] | "mkdf" | ID of core/stick | | `NAME1` | r | r | 4B | char[4] | "mkdf" | ID of core/stick |
| `VERSION` | r | r | 4B | u32 | 1 | Current version. | | `VERSION` | r | r | 4B | u32 | 1 | Current version. |
| `SWITCH_APP` | r/w | r | 1B | u8 | | Write anything here to trigger the switch to application mode. Reading | | `SYSTEM_MODE_CTRL` | r/w | r | 1B | u8 | | Write anything here to trigger the switch to application mode. Reading |
| | | | | | | returns 0 if device is in firmware mode, 0xffffffff if in app mode. | | | | | | | | returns 0 if device is in firmware mode, 0xffffffff if in app mode. |
| `LED` | r/w | r/w | 1B | u8 | | Control of the color LEDs in RBG LED on the board. | | `LED` | r/w | r/w | 1B | u8 | | Control of the color LEDs in RBG LED on the board. |
| | | | | | | Bit 0 is Blue, bit 1 is Green, and bit 2 is Red LED. | | | | | | | | Bit 0 is Blue, bit 1 is Green, and bit 2 is Red LED. |

2
hw/application_fpga/application_fpga.bin.sha256
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@ -1 +1 @@
6585aafa13727dc5bf560f34c457048ca3d13ee6ab502c2afc737b1e70fa5a00 application_fpga.bin f28a9b5585b34f050f959159efd926164357bc6a2e9479531e9b87e6222671e2 application_fpga.bin

5
hw/application_fpga/core/fw_ram/README.md
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@ -21,5 +21,6 @@ The contents of the fw_ram is cleared when the FPGA is powered up and
configured by the bitstream. The contents is not cleared by a system configured by the bitstream. The contents is not cleared by a system
reset. reset.
If the fw_app_mode input is set, no memory accesses are allowed. Any If the system_mode input is set, i.e. in firmware mode, no memory
reads when the fw_app_mode is set will retun an all zero word. accesses are allowed. Any reads when the system_mode is set will
return an all zero word.

24
hw/application_fpga/core/fw_ram/rtl/fw_ram.v
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@ -17,7 +17,7 @@ module fw_ram (
input wire clk, input wire clk,
input wire reset_n, input wire reset_n,
input wire fw_app_mode, input wire system_mode,
input wire cs, input wire cs,
input wire [ 3 : 0] we, input wire [ 3 : 0] we,
@ -35,7 +35,7 @@ module fw_ram (
reg [31 : 0] mem_read_data0; reg [31 : 0] mem_read_data0;
reg [31 : 0] mem_read_data1; reg [31 : 0] mem_read_data1;
reg ready_reg; reg ready_reg;
wire fw_app_cs; wire system_mode_cs;
reg bank0; reg bank0;
reg bank1; reg bank1;
@ -45,7 +45,7 @@ module fw_ram (
//---------------------------------------------------------------- //----------------------------------------------------------------
assign read_data = tmp_read_data; assign read_data = tmp_read_data;
assign ready = ready_reg; assign ready = ready_reg;
assign fw_app_cs = cs && ~fw_app_mode; assign system_mode_cs = cs && ~system_mode;
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -56,12 +56,12 @@ module fw_ram (
.RADDR({3'h0, address[7 : 0]}), .RADDR({3'h0, address[7 : 0]}),
.RCLK(clk), .RCLK(clk),
.RCLKE(1'h1), .RCLKE(1'h1),
.RE(fw_app_cs & bank0), .RE(system_mode_cs & bank0),
.WADDR({3'h0, address[7 : 0]}), .WADDR({3'h0, address[7 : 0]}),
.WCLK(clk), .WCLK(clk),
.WCLKE(1'h1), .WCLKE(1'h1),
.WDATA(write_data[15 : 0]), .WDATA(write_data[15 : 0]),
.WE((|we & fw_app_cs & bank0)), .WE((|we & system_mode_cs & bank0)),
.MASK({{8{~we[1]}}, {8{~we[0]}}}) .MASK({{8{~we[1]}}, {8{~we[0]}}})
); );
@ -70,12 +70,12 @@ module fw_ram (
.RADDR({3'h0, address[7 : 0]}), .RADDR({3'h0, address[7 : 0]}),
.RCLK(clk), .RCLK(clk),
.RCLKE(1'h1), .RCLKE(1'h1),
.RE(fw_app_cs & bank0), .RE(system_mode_cs & bank0),
.WADDR({3'h0, address[7 : 0]}), .WADDR({3'h0, address[7 : 0]}),
.WCLK(clk), .WCLK(clk),
.WCLKE(1'h1), .WCLKE(1'h1),
.WDATA(write_data[31 : 16]), .WDATA(write_data[31 : 16]),
.WE((|we & fw_app_cs & bank0)), .WE((|we & system_mode_cs & bank0)),
.MASK({{8{~we[3]}}, {8{~we[2]}}}) .MASK({{8{~we[3]}}, {8{~we[2]}}})
); );
@ -85,12 +85,12 @@ module fw_ram (
.RADDR({3'h0, address[7 : 0]}), .RADDR({3'h0, address[7 : 0]}),
.RCLK(clk), .RCLK(clk),
.RCLKE(1'h1), .RCLKE(1'h1),
.RE(fw_app_cs & bank1), .RE(system_mode_cs & bank1),
.WADDR({3'h0, address[7 : 0]}), .WADDR({3'h0, address[7 : 0]}),
.WCLK(clk), .WCLK(clk),
.WCLKE(1'h1), .WCLKE(1'h1),
.WDATA(write_data[15 : 0]), .WDATA(write_data[15 : 0]),
.WE((|we & fw_app_cs & bank1)), .WE((|we & system_mode_cs & bank1)),
.MASK({{8{~we[1]}}, {8{~we[0]}}}) .MASK({{8{~we[1]}}, {8{~we[0]}}})
); );
@ -99,12 +99,12 @@ module fw_ram (
.RADDR({3'h0, address[7 : 0]}), .RADDR({3'h0, address[7 : 0]}),
.RCLK(clk), .RCLK(clk),
.RCLKE(1'h1), .RCLKE(1'h1),
.RE(fw_app_cs & bank1), .RE(system_mode_cs & bank1),
.WADDR({3'h0, address[7 : 0]}), .WADDR({3'h0, address[7 : 0]}),
.WCLK(clk), .WCLK(clk),
.WCLKE(1'h1), .WCLKE(1'h1),
.WDATA(write_data[31 : 16]), .WDATA(write_data[31 : 16]),
.WE((|we & fw_app_cs & bank1)), .WE((|we & system_mode_cs & bank1)),
.MASK({{8{~we[3]}}, {8{~we[2]}}}) .MASK({{8{~we[3]}}, {8{~we[2]}}})
); );
@ -129,7 +129,7 @@ module fw_ram (
bank1 = 1'h0; bank1 = 1'h0;
tmp_read_data = 32'h0; tmp_read_data = 32'h0;
if (fw_app_cs) begin if (system_mode_cs) begin
if (address[8]) begin if (address[8]) begin
bank1 = 1'h1; bank1 = 1'h1;
tmp_read_data = mem_read_data1; tmp_read_data = mem_read_data1;

8
hw/application_fpga/core/tk1/README.md
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@ -26,7 +26,7 @@ applications.
### Control of execution mode ### Control of execution mode
``` ```
ADDR_SWITCH_APP: 0x08 ADDR_SYSTEM_MODE_CTRL: 0x08
``` ```
This register controls if the device is executing in FW mode or in App This register controls if the device is executing in FW mode or in App
@ -75,7 +75,7 @@ corresponding register is one or zero.
These registers provide read only information to the loaded app to These registers provide read only information to the loaded app to
itself - where it was loaded and its size. The values are written by itself - where it was loaded and its size. The values are written by
FW as part of the loading of the app. The registers can't be written FW as part of the loading of the app. The registers can't be written
when the ADDR_SWITCH_APP has been set. when the ADDR_SYSTEM_MODE_CTRL has been set.
### Access to Blake2s ### Access to Blake2s
@ -86,7 +86,7 @@ when the ADDR_SWITCH_APP has been set.
This register provides the 32-bit function pointer address to the This register provides the 32-bit function pointer address to the
Blake2s hash function in the FW. It is written by FW during boot. The Blake2s hash function in the FW. It is written by FW during boot. The
register can't be written to when the ADDR_SWITCH_APP has been set. register can't be written to when the ADDR_SYSTEM_MODE_CTRL has been set.
### Access to CDI ### Access to CDI
@ -99,7 +99,7 @@ register can't be written to when the ADDR_SWITCH_APP has been set.
These registers provide access to the 256-bit compound device secret These registers provide access to the 256-bit compound device secret
calculated by the FW as part of loading an application. The registers calculated by the FW as part of loading an application. The registers
are written by the FW. The register can't be written to when the are written by the FW. The register can't be written to when the
ADDR_SWITCH_APP has been set. Apps can read the CDI and is it as base ADDR_SYSTEM_MODE_CTRL has been set. Apps can read the CDI and is it as base
secret for any secrets it needs to perform its intended use case. secret for any secrets it needs to perform its intended use case.

40
hw/application_fpga/core/tk1/rtl/tk1.v
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@ -18,7 +18,7 @@ module tk1 (
input wire reset_n, input wire reset_n,
input wire cpu_trap, input wire cpu_trap,
output wire fw_app_mode, output wire system_mode,
input wire [31 : 0] cpu_addr, input wire [31 : 0] cpu_addr,
input wire cpu_instr, input wire cpu_instr,
@ -59,7 +59,7 @@ module tk1 (
localparam ADDR_NAME1 = 8'h01; localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02; localparam ADDR_VERSION = 8'h02;
localparam ADDR_SWITCH_APP = 8'h08; localparam ADDR_SYSTEM_MODE_CTRL = 8'h08;
localparam ADDR_LED = 8'h09; localparam ADDR_LED = 8'h09;
localparam LED_R_BIT = 2; localparam LED_R_BIT = 2;
@ -112,8 +112,8 @@ module tk1 (
reg [31 : 0] cdi_mem [0 : 7]; reg [31 : 0] cdi_mem [0 : 7];
reg cdi_mem_we; reg cdi_mem_we;
reg switch_app_reg; reg system_mode_reg;
reg switch_app_we; reg system_mode_we;
reg [ 2 : 0] led_reg; reg [ 2 : 0] led_reg;
reg led_we; reg led_we;
@ -185,7 +185,7 @@ module tk1 (
assign read_data = tmp_read_data; assign read_data = tmp_read_data;
assign ready = tmp_ready; assign ready = tmp_ready;
assign fw_app_mode = switch_app_reg; assign system_mode = system_mode_reg;
assign force_trap = force_trap_reg; assign force_trap = force_trap_reg;
@ -248,7 +248,7 @@ module tk1 (
//---------------------------------------------------------------- //----------------------------------------------------------------
always @(posedge clk) begin : reg_update always @(posedge clk) begin : reg_update
if (!reset_n) begin if (!reset_n) begin
switch_app_reg <= 1'h0; system_mode_reg <= 1'h0;
led_reg <= 3'h6; led_reg <= 3'h6;
gpio1_reg <= 2'h0; gpio1_reg <= 2'h0;
gpio2_reg <= 2'h0; gpio2_reg <= 2'h0;
@ -287,8 +287,8 @@ module tk1 (
gpio2_reg[0] <= gpio2; gpio2_reg[0] <= gpio2;
gpio2_reg[1] <= gpio2_reg[0]; gpio2_reg[1] <= gpio2_reg[0];
if (switch_app_we) begin if (system_mode_we) begin
switch_app_reg <= 1'h1; system_mode_reg <= 1'h1;
end end
if (led_we) begin if (led_we) begin
@ -414,7 +414,7 @@ module tk1 (
// api // api
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* begin : api always @* begin : api
switch_app_we = 1'h0; system_mode_we = 1'h0;
led_we = 1'h0; led_we = 1'h0;
gpio3_we = 1'h0; gpio3_we = 1'h0;
gpio4_we = 1'h0; gpio4_we = 1'h0;
@ -443,8 +443,8 @@ module tk1 (
if (cs) begin if (cs) begin
tmp_ready = 1'h1; tmp_ready = 1'h1;
if (we) begin if (we) begin
if (address == ADDR_SWITCH_APP) begin if (address == ADDR_SYSTEM_MODE_CTRL) begin
switch_app_we = 1'h1; system_mode_we = 1'h1;
end end
if (address == ADDR_LED) begin if (address == ADDR_LED) begin
@ -457,13 +457,13 @@ module tk1 (
end end
if (address == ADDR_APP_START) begin if (address == ADDR_APP_START) begin
if (!switch_app_reg) begin if (!system_mode_reg) begin
app_start_we = 1'h1; app_start_we = 1'h1;
end end
end end
if (address == ADDR_APP_SIZE) begin if (address == ADDR_APP_SIZE) begin
if (!switch_app_reg) begin if (!system_mode_reg) begin
app_size_we = 1'h1; app_size_we = 1'h1;
end end
end end
@ -473,25 +473,25 @@ module tk1 (
end end
if (address == ADDR_BLAKE2S) begin if (address == ADDR_BLAKE2S) begin
if (!switch_app_reg) begin if (!system_mode_reg) begin
blake2s_addr_we = 1'h1; blake2s_addr_we = 1'h1;
end end
end end
if ((address >= ADDR_CDI_FIRST) && (address <= ADDR_CDI_LAST)) begin if ((address >= ADDR_CDI_FIRST) && (address <= ADDR_CDI_LAST)) begin
if (!switch_app_reg) begin if (!system_mode_reg) begin
cdi_mem_we = 1'h1; cdi_mem_we = 1'h1;
end end
end end
if (address == ADDR_RAM_ADDR_RAND) begin if (address == ADDR_RAM_ADDR_RAND) begin
if (!switch_app_reg) begin if (!system_mode_reg) begin
ram_addr_rand_we = 1'h1; ram_addr_rand_we = 1'h1;
end end
end end
if (address == ADDR_RAM_DATA_RAND) begin if (address == ADDR_RAM_DATA_RAND) begin
if (!switch_app_reg) begin if (!system_mode_reg) begin
ram_data_rand_we = 1'h1; ram_data_rand_we = 1'h1;
end end
end end
@ -538,8 +538,8 @@ module tk1 (
tmp_read_data = TK1_VERSION; tmp_read_data = TK1_VERSION;
end end
if (address == ADDR_SWITCH_APP) begin if (address == ADDR_SYSTEM_MODE_CTRL) begin
tmp_read_data = {32{switch_app_reg}}; tmp_read_data = {32{system_mode_reg}};
end end
if (address == ADDR_LED) begin if (address == ADDR_LED) begin
@ -567,7 +567,7 @@ module tk1 (
end end
if ((address >= ADDR_UDI_FIRST) && (address <= ADDR_UDI_LAST)) begin if ((address >= ADDR_UDI_FIRST) && (address <= ADDR_UDI_LAST)) begin
if (!switch_app_reg) begin if (!system_mode_reg) begin
tmp_read_data = udi_rdata; tmp_read_data = udi_rdata;
end end
end end

16
hw/application_fpga/core/tk1/tb/tb_tk1.v
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@ -27,7 +27,7 @@ module tb_tk1 ();
localparam ADDR_NAME1 = 8'h01; localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02; localparam ADDR_VERSION = 8'h02;
localparam ADDR_SWITCH_APP = 8'h08; localparam ADDR_SYSTEM_MODE_CTRL = 8'h08;
localparam ADDR_LED = 8'h09; localparam ADDR_LED = 8'h09;
localparam LED_R_BIT = 2; localparam LED_R_BIT = 2;
@ -76,7 +76,7 @@ module tb_tk1 ();
reg tb_clk; reg tb_clk;
reg tb_reset_n; reg tb_reset_n;
reg tb_cpu_trap; reg tb_cpu_trap;
wire tb_fw_app_mode; wire tb_system_mode;
reg [31 : 0] tb_cpu_addr; reg [31 : 0] tb_cpu_addr;
reg tb_cpu_instr; reg tb_cpu_instr;
@ -122,7 +122,7 @@ module tb_tk1 ();
.reset_n(tb_reset_n), .reset_n(tb_reset_n),
.cpu_trap(tb_cpu_trap), .cpu_trap(tb_cpu_trap),
.fw_app_mode(tb_fw_app_mode), .system_mode(tb_system_mode),
.cpu_addr (tb_cpu_addr), .cpu_addr (tb_cpu_addr),
.cpu_instr (tb_cpu_instr), .cpu_instr (tb_cpu_instr),
@ -192,7 +192,7 @@ module tb_tk1 ();
$display("------------"); $display("------------");
if (tb_main_monitor) begin if (tb_main_monitor) begin
$display("Inputs and outputs:"); $display("Inputs and outputs:");
$display("tb_cpu_trap: 0x%1x, fw_app_mode: 0x%1x", tb_cpu_trap, tb_fw_app_mode); $display("tb_cpu_trap: 0x%1x, system_mode: 0x%1x", tb_cpu_trap, tb_system_mode);
$display("cpu_addr: 0x%08x, cpu_instr: 0x%1x, cpu_valid: 0x%1x, force_tap: 0x%1x", $display("cpu_addr: 0x%08x, cpu_instr: 0x%1x, cpu_valid: 0x%1x, force_tap: 0x%1x",
tb_cpu_addr, tb_cpu_instr, tb_cpu_valid, tb_force_trap); tb_cpu_addr, tb_cpu_instr, tb_cpu_valid, tb_force_trap);
$display("ram_addr_rand: 0x%08x, ram_data_rand: 0x%08x", tb_ram_addr_rand, $display("ram_addr_rand: 0x%08x, ram_data_rand: 0x%08x", tb_ram_addr_rand,
@ -441,7 +441,7 @@ module tb_tk1 ();
read_check_word(ADDR_CDI_LAST + 0, 32'h70717273); read_check_word(ADDR_CDI_LAST + 0, 32'h70717273);
$display("--- test3: Switch to app mode."); $display("--- test3: Switch to app mode.");
write_word(ADDR_SWITCH_APP, 32'hdeadbeef); write_word(ADDR_SYSTEM_MODE_CTRL, 32'hdeadbeef);
$display("--- test3: Try to write CDI again."); $display("--- test3: Try to write CDI again.");
write_word(ADDR_CDI_FIRST + 0, 32'hfffefdfc); write_word(ADDR_CDI_FIRST + 0, 32'hfffefdfc);
@ -489,7 +489,7 @@ module tb_tk1 ();
read_check_word(ADDR_BLAKE2S, 32'hcafebabe); read_check_word(ADDR_BLAKE2S, 32'hcafebabe);
$display("--- test4: Switch to app mode."); $display("--- test4: Switch to app mode.");
write_word(ADDR_SWITCH_APP, 32'hf00ff00f); write_word(ADDR_SYSTEM_MODE_CTRL, 32'hf00ff00f);
$display("--- test4: Write Blake2s entry point again."); $display("--- test4: Write Blake2s entry point again.");
write_word(ADDR_BLAKE2S, 32'hdeadbeef); write_word(ADDR_BLAKE2S, 32'hdeadbeef);
@ -525,7 +525,7 @@ module tb_tk1 ();
read_check_word(ADDR_APP_SIZE, 32'h47114711); read_check_word(ADDR_APP_SIZE, 32'h47114711);
$display("--- test5: Switch to app mode."); $display("--- test5: Switch to app mode.");
write_word(ADDR_SWITCH_APP, 32'hf000000); write_word(ADDR_SYSTEM_MODE_CTRL, 32'hf000000);
$display("--- test5: Write app start address and size again."); $display("--- test5: Write app start address and size again.");
write_word(ADDR_APP_START, 32'hdeadbeef); write_word(ADDR_APP_START, 32'hdeadbeef);
@ -564,7 +564,7 @@ module tb_tk1 ();
dut.ram_addr_rand, dut.ram_data_rand); dut.ram_addr_rand, dut.ram_data_rand);
$display("--- test6: Switch to app mode."); $display("--- test6: Switch to app mode.");
write_word(ADDR_SWITCH_APP, 32'hf000000); write_word(ADDR_SYSTEM_MODE_CTRL, 32'hf000000);
$display("--- test6: Write to ADDR_RAM_ADDR_RAND and ADDR_RAM_DATA_RAND again."); $display("--- test6: Write to ADDR_RAM_ADDR_RAND and ADDR_RAM_DATA_RAND again.");
write_word(ADDR_RAM_ADDR_RAND, 32'hdeadbeef); write_word(ADDR_RAM_ADDR_RAND, 32'hdeadbeef);

2
hw/application_fpga/core/uds/README.md
View File

@ -6,7 +6,7 @@ Unique Device Secret core
This core store and protect the Unique Device Secret (UDS) asset. The This core store and protect the Unique Device Secret (UDS) asset. The
UDS can be accessed as eight separate 32-bit words. The words can only UDS can be accessed as eight separate 32-bit words. The words can only
be accessed as long as the fw_app_mode input is low, implying that the be accessed as long as the system_mode input is low, implying that the
CPU is executing the FW. CPU is executing the FW.
The UDS words can be accessed in any order, but a given word can only The UDS words can be accessed in any order, but a given word can only

4
hw/application_fpga/core/uds/rtl/uds.v
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@ -17,7 +17,7 @@ module uds (
input wire clk, input wire clk,
input wire reset_n, input wire reset_n,
input wire fw_app_mode, input wire system_mode,
input wire cs, input wire cs,
input wire [ 2 : 0] address, input wire [ 2 : 0] address,
@ -89,7 +89,7 @@ module uds (
if (cs) begin if (cs) begin
tmp_ready = 1'h1; tmp_ready = 1'h1;
if (!fw_app_mode) begin if (!system_mode) begin
if (uds_rd_reg[address[2 : 0]] == 1'h0) begin if (uds_rd_reg[address[2 : 0]] == 1'h0) begin
uds_rd_we = 1'h1; uds_rd_we = 1'h1;
end end

8
hw/application_fpga/core/uds/tb/tb_uds.v
View File

@ -37,7 +37,7 @@ module tb_uds ();
reg tb_clk; reg tb_clk;
reg tb_reset_n; reg tb_reset_n;
reg tb_fw_app_mode; reg tb_system_mode;
reg tb_cs; reg tb_cs;
reg [ 7 : 0] tb_address; reg [ 7 : 0] tb_address;
wire [31 : 0] tb_read_data; wire [31 : 0] tb_read_data;
@ -50,7 +50,7 @@ module tb_uds ();
.clk(tb_clk), .clk(tb_clk),
.reset_n(tb_reset_n), .reset_n(tb_reset_n),
.fw_app_mode(tb_fw_app_mode), .system_mode(tb_system_mode),
.cs(tb_cs), .cs(tb_cs),
.address(tb_address), .address(tb_address),
@ -95,7 +95,7 @@ module tb_uds ();
$display("State of DUT at cycle: %08d", cycle_ctr); $display("State of DUT at cycle: %08d", cycle_ctr);
$display("------------"); $display("------------");
$display("Inputs and outputs:"); $display("Inputs and outputs:");
$display("fw_app_mode: 0x%1x", tb_fw_app_mode); $display("system_mode: 0x%1x", tb_system_mode);
$display("cs: 0x%1x, address: 0x%02x, read_data: 0x%08x", tb_cs, tb_address, tb_read_data); $display("cs: 0x%1x, address: 0x%02x, read_data: 0x%08x", tb_cs, tb_address, tb_read_data);
$display(""); $display("");
@ -160,7 +160,7 @@ module tb_uds ();
tb_clk = 1'h0; tb_clk = 1'h0;
tb_reset_n = 1'h1; tb_reset_n = 1'h1;
tb_fw_app_mode = 1'h0; tb_system_mode = 1'h0;
tb_cs = 1'h0; tb_cs = 1'h0;
tb_address = 8'h0; tb_address = 8'h0;
end end

2
hw/application_fpga/fw/README.md
View File

@ -188,7 +188,7 @@ Typical expected use scenario:
more automatic variables. more automatic variables.
8. Firmware starts the application by first switching to from 8. Firmware starts the application by first switching to from
firmware mode to application mode by writing to the `SWITCH_APP` firmware mode to application mode by writing to the `SYSTEM_MODE_CTRL`
register. In this mode the MMIO region is restricted, e.g. some register. In this mode the MMIO region is restricted, e.g. some
registers are removed (`UDS`), and some are switched from registers are removed (`UDS`), and some are switched from
read/write to read-only (see [the memory read/write to read-only (see [the memory

12
hw/application_fpga/fw/testfw/main.c
View File

@ -15,7 +15,7 @@ volatile uint32_t *tk1name1 = (volatile uint32_t *)TK1_MMIO_TK1_NAME1;
volatile uint32_t *uds = (volatile uint32_t *)TK1_MMIO_UDS_FIRST; volatile uint32_t *uds = (volatile uint32_t *)TK1_MMIO_UDS_FIRST;
volatile uint32_t *cdi = (volatile uint32_t *)TK1_MMIO_TK1_CDI_FIRST; volatile uint32_t *cdi = (volatile uint32_t *)TK1_MMIO_TK1_CDI_FIRST;
volatile uint32_t *udi = (volatile uint32_t *)TK1_MMIO_TK1_UDI_FIRST; volatile uint32_t *udi = (volatile uint32_t *)TK1_MMIO_TK1_UDI_FIRST;
volatile uint32_t *switch_app = (volatile uint32_t *)TK1_MMIO_TK1_SWITCH_APP; volatile uint32_t *system_mode_ctrl = (volatile uint32_t *)TK1_MMIO_TK1_SYSTEM_MODE_CTRL;
volatile uint8_t *fw_ram = (volatile uint8_t *)TK1_MMIO_FW_RAM_BASE; volatile uint8_t *fw_ram = (volatile uint8_t *)TK1_MMIO_FW_RAM_BASE;
volatile uint32_t *timer = (volatile uint32_t *)TK1_MMIO_TIMER_TIMER; volatile uint32_t *timer = (volatile uint32_t *)TK1_MMIO_TIMER_TIMER;
volatile uint32_t *timer_prescaler = (volatile uint32_t *)TK1_MMIO_TIMER_PRESCALER; volatile uint32_t *timer_prescaler = (volatile uint32_t *)TK1_MMIO_TIMER_PRESCALER;
@ -257,9 +257,9 @@ int main(void)
} }
} }
uint32_t sw = *switch_app; uint32_t sw = *system_mode_ctrl;
if (sw != 0) { if (sw != 0) {
failmsg("switch_app is not 0 in fw mode"); failmsg("system_mode_ctrl is not 0 in fw mode");
anyfailed = 1; anyfailed = 1;
} }
@ -269,11 +269,11 @@ int main(void)
// Turn on application mode. // Turn on application mode.
// ------------------------- // -------------------------
*switch_app = 1; *system_mode_ctrl = 1;
sw = *switch_app; sw = *system_mode_ctrl;
if (sw != 0xffffffff) { if (sw != 0xffffffff) {
failmsg("switch_app is not 0xffffffff in app mode"); failmsg("system_mode_ctrl is not 0xffffffff in app mode");
anyfailed = 1; anyfailed = 1;
} }

4
hw/application_fpga/fw/tk1/main.c
View File

@ -13,7 +13,7 @@
// clang-format off // clang-format off
static volatile uint32_t *uds = (volatile uint32_t *)TK1_MMIO_UDS_FIRST; static volatile uint32_t *uds = (volatile uint32_t *)TK1_MMIO_UDS_FIRST;
static volatile uint32_t *switch_app = (volatile uint32_t *)TK1_MMIO_TK1_SWITCH_APP; static volatile uint32_t *system_mode_ctrl = (volatile uint32_t *)TK1_MMIO_TK1_SYSTEM_MODE_CTRL;
static volatile uint32_t *name0 = (volatile uint32_t *)TK1_MMIO_TK1_NAME0; static volatile uint32_t *name0 = (volatile uint32_t *)TK1_MMIO_TK1_NAME0;
static volatile uint32_t *name1 = (volatile uint32_t *)TK1_MMIO_TK1_NAME1; static volatile uint32_t *name1 = (volatile uint32_t *)TK1_MMIO_TK1_NAME1;
static volatile uint32_t *ver = (volatile uint32_t *)TK1_MMIO_TK1_VERSION; static volatile uint32_t *ver = (volatile uint32_t *)TK1_MMIO_TK1_VERSION;
@ -343,7 +343,7 @@ static void run(const struct context *ctx)
// clang-format on // clang-format on
// Flip over to application mode // Flip over to application mode
*switch_app = 1; *system_mode_ctrl = 1;
// XXX Firmware stack now no longer available // XXX Firmware stack now no longer available
// Don't use any function calls! // Don't use any function calls!

2
hw/application_fpga/fw/tk1_mem.h
View File

@ -109,7 +109,9 @@
#define TK1_MMIO_TK1_NAME1 0xff000004 #define TK1_MMIO_TK1_NAME1 0xff000004
#define TK1_MMIO_TK1_VERSION 0xff000008 #define TK1_MMIO_TK1_VERSION 0xff000008
// Deprecated - use _SYSTEM_MODE_CTRL instead
#define TK1_MMIO_TK1_SWITCH_APP 0xff000020 #define TK1_MMIO_TK1_SWITCH_APP 0xff000020
#define TK1_MMIO_TK1_SYSTEM_MODE_CTRL 0xff000020
#define TK1_MMIO_TK1_LED 0xff000024 #define TK1_MMIO_TK1_LED 0xff000024
#define TK1_MMIO_TK1_LED_R_BIT 2 #define TK1_MMIO_TK1_LED_R_BIT 2

8
hw/application_fpga/rtl/application_fpga.v
View File

@ -142,7 +142,7 @@ module application_fpga (
reg [31 : 0] tk1_write_data; reg [31 : 0] tk1_write_data;
wire [31 : 0] tk1_read_data; wire [31 : 0] tk1_read_data;
wire tk1_ready; wire tk1_ready;
wire fw_app_mode; wire system_mode;
wire force_trap; wire force_trap;
wire [14 : 0] ram_addr_rand; wire [14 : 0] ram_addr_rand;
wire [31 : 0] ram_data_rand; wire [31 : 0] ram_data_rand;
@ -237,7 +237,7 @@ module application_fpga (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.fw_app_mode(fw_app_mode), .system_mode(system_mode),
.cs(fw_ram_cs), .cs(fw_ram_cs),
.we(fw_ram_we), .we(fw_ram_we),
@ -277,7 +277,7 @@ module application_fpga (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.fw_app_mode(fw_app_mode), .system_mode(system_mode),
.cs(uds_cs), .cs(uds_cs),
.address(uds_address), .address(uds_address),
@ -320,7 +320,7 @@ module application_fpga (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.fw_app_mode(fw_app_mode), .system_mode(system_mode),
.cpu_addr (cpu_addr), .cpu_addr (cpu_addr),
.cpu_instr (cpu_instr), .cpu_instr (cpu_instr),

4
hw/application_fpga/tb/application_fpga_vsim.v
View File

@ -152,7 +152,7 @@ module application_fpga (
reg [31 : 0] tk1_write_data; reg [31 : 0] tk1_write_data;
wire [31 : 0] tk1_read_data; wire [31 : 0] tk1_read_data;
wire tk1_ready; wire tk1_ready;
wire fw_app_mode; wire system_mode;
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -304,7 +304,7 @@ module application_fpga (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.fw_app_mode(fw_app_mode), .system_mode(system_mode),
.led_r(led_r), .led_r(led_r),
.led_g(led_g), .led_g(led_g),