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Harmonize the naming of firmware and app mode.
- The API changes name from `_SWITCH_APP` to `_SYSTEM_MODE_CTRL`. - The registers and wires changes name to `system_mode_*`, instead of a mix of `switch_app_*` and `fw_app_mode`.
This commit is contained in:
Jonas Thörnblad
Daniel Jobson
parent
69ef6dde8b
commit
aea2e319eb
16 changed files with 149 additions and 146 deletions
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@ -227,51 +227,51 @@ Assigned core prefixes:
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*Nota bene*: MMIO accesses should be 32 bit wide, e.g use `lw` and
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`sw`. Exceptions are `UDS`, `FW_RAM` and `QEMU_DEBUG`.
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| *name* | *fw* | *app* | *size* | *type* | *content* | *description* |
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|-------------------|-------|-----------|--------|----------|-----------|-------------------------------------------------------------------------|
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| `TRNG_STATUS` | r | r | | | | TRNG_STATUS_READY_BIT is 1 when an entropy word is available. |
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| `TRNG_ENTROPY` | r | r | 4B | u32 | | Entropy word. Reading a word will clear status. |
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| `TIMER_CTRL` | r/w | r/w | | | | If TIMER_STATUS_RUNNING_BIT in TIMER_STATUS is 0, setting |
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| | | | | | | TIMER_CTRL_START_BIT here starts the timer. |
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| | | | | | | If TIMER_STATUS_RUNNING_BIT in TIMER_STATUS is 1, setting |
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| | | | | | | TIMER_CTRL_STOP_BIT here stops the timer. |
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| `TIMER_STATUS` | r | r | | | | TIMER_STATUS_RUNNING_BIT is 1 when the timer is running. |
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| `TIMER_PRESCALER` | r/w | r/w | 4B | | | Prescaler init value. Write blocked when running. |
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| `TIMER_TIMER` | r/w | r/w | 4B | | | Timer init or current value while running. Write blocked when running. |
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| `UDS_FIRST` | r[^3] | invisible | 4B | u8[32] | | First word of Unique Device Secret key. Note: Read once per power up. |
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| `UDS_LAST` | | invisible | | | | The last word of the UDS. Note: Read once per power up. |
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| `UART_BITRATE` | r/w | | | | | TBD |
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| `UART_DATABITS` | r/w | | | | | TBD |
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| `UART_STOPBITS` | r/w | | | | | TBD |
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| `UART_RX_STATUS` | r | r | 1B | u8 | | Non-zero when there is data to read |
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| `UART_RX_DATA` | r | r | 1B | u8 | | Data to read. Only LSB contains data |
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| `UART_RX_BYTES` | r | r | 4B | u32 | | Number of bytes received from the host and not yet read by SW, FW. |
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| `UART_TX_STATUS` | r | r | 1B | u8 | | Non-zero when it's OK to write data to send. |
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| `UART_TX_DATA` | w | w | 1B | u8 | | Data to send. Only LSB contains data |
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| `TOUCH_STATUS` | r/w | r/w | | | | TOUCH_STATUS_EVENT_BIT is 1 when touched. After detecting a touch |
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| | | | | | | event (reading a 1), write anything here to acknowledge it. |
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| `FW_RAM` | r/w | invisible | 2 kiB | u8[2048] | | Firmware-only RAM. |
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| `UDI` | r | invisible | 8B | u64 | | Unique Device ID (UDI). |
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| `QEMU_DEBUG` | w | w | | u8 | | Debug console (only in QEMU) |
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| `NAME0` | r | r | 4B | char[4] | "tk1 " | ID of core/stick |
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| `NAME1` | r | r | 4B | char[4] | "mkdf" | ID of core/stick |
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| `VERSION` | r | r | 4B | u32 | 1 | Current version. |
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| `SWITCH_APP` | r/w | r | 1B | u8 | | Write anything here to trigger the switch to application mode. Reading |
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| | | | | | | returns 0 if device is in firmware mode, 0xffffffff if in app mode. |
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| `LED` | r/w | r/w | 1B | u8 | | Control of the color LEDs in RBG LED on the board. |
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| | | | | | | Bit 0 is Blue, bit 1 is Green, and bit 2 is Red LED. |
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| `GPIO` | r/w | r/w | 1B | u8 | | Bits 0 and 1 contain the input level of GPIO 1 and 2. |
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| | | | | u8 | | Bits 3 and 4 store the output level of GPIO 3 and 4. |
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| `APP_ADDR` | r/w | r | 4B | u32 | | Firmware stores app load address here, so app can read its own location |
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| `APP_SIZE` | r/w | r | 4B | u32 | | Firmware stores app app size here, so app can read its own size |
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| `BLAKE2S` | r/w | r | 4B | u32 | | Function pointer to a BLAKE2S function in the firmware |
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| `CDI_FIRST` | r/w | r | 32B | u8[32] | | Compound Device Identifier (CDI). UDS+measurement... |
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| `CDI_LAST` | | r | | | | Last word of CDI |
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| `RAM_ASLR` | w | invisible | 4B | u32 | | Address Space Randomization seed value for the RAM |
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| `RAM_SCRAMBLE` | w | invisible | 4B | u32 | | Data scrambling seed value for the RAM |
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| `CPU_MON_CTRL` | w | w | 4B | u32 | | Bit 0 enables CPU execution monitor. Can't be unset. Lock adresses |
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| `CPU_MON_FIRST` | w | w | 4B | u32 | | First address of the area monitored for execution attempts |
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| `CPU_MON_LAST` | w | w | 4B | u32 | | Last address of the area monitored for execution attempts |
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| *name* | *fw* | *app* | *size* | *type* | *content* | *description* |
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|--------------------|-------|-----------|--------|----------|-----------|-------------------------------------------------------------------------|
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| `TRNG_STATUS` | r | r | | | | TRNG_STATUS_READY_BIT is 1 when an entropy word is available. |
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| `TRNG_ENTROPY` | r | r | 4B | u32 | | Entropy word. Reading a word will clear status. |
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| `TIMER_CTRL` | r/w | r/w | | | | If TIMER_STATUS_RUNNING_BIT in TIMER_STATUS is 0, setting |
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| | | | | | | TIMER_CTRL_START_BIT here starts the timer. |
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| | | | | | | If TIMER_STATUS_RUNNING_BIT in TIMER_STATUS is 1, setting |
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| | | | | | | TIMER_CTRL_STOP_BIT here stops the timer. |
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| `TIMER_STATUS` | r | r | | | | TIMER_STATUS_RUNNING_BIT is 1 when the timer is running. |
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| `TIMER_PRESCALER` | r/w | r/w | 4B | | | Prescaler init value. Write blocked when running. |
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| `TIMER_TIMER` | r/w | r/w | 4B | | | Timer init or current value while running. Write blocked when running. |
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| `UDS_FIRST` | r[^3] | invisible | 4B | u8[32] | | First word of Unique Device Secret key. Note: Read once per power up. |
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| `UDS_LAST` | | invisible | | | | The last word of the UDS. Note: Read once per power up. |
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| `UART_BITRATE` | r/w | | | | | TBD |
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| `UART_DATABITS` | r/w | | | | | TBD |
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| `UART_STOPBITS` | r/w | | | | | TBD |
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| `UART_RX_STATUS` | r | r | 1B | u8 | | Non-zero when there is data to read |
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| `UART_RX_DATA` | r | r | 1B | u8 | | Data to read. Only LSB contains data |
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| `UART_RX_BYTES` | r | r | 4B | u32 | | Number of bytes received from the host and not yet read by SW, FW. |
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| `UART_TX_STATUS` | r | r | 1B | u8 | | Non-zero when it's OK to write data to send. |
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| `UART_TX_DATA` | w | w | 1B | u8 | | Data to send. Only LSB contains data |
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| `TOUCH_STATUS` | r/w | r/w | | | | TOUCH_STATUS_EVENT_BIT is 1 when touched. After detecting a touch |
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| | | | | | | event (reading a 1), write anything here to acknowledge it. |
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| `FW_RAM` | r/w | invisible | 2 kiB | u8[2048] | | Firmware-only RAM. |
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| `UDI` | r | invisible | 8B | u64 | | Unique Device ID (UDI). |
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| `QEMU_DEBUG` | w | w | | u8 | | Debug console (only in QEMU) |
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| `NAME0` | r | r | 4B | char[4] | "tk1 " | ID of core/stick |
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| `NAME1` | r | r | 4B | char[4] | "mkdf" | ID of core/stick |
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| `VERSION` | r | r | 4B | u32 | 1 | Current version. |
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| `SYSTEM_MODE_CTRL` | r/w | r | 1B | u8 | | Write anything here to trigger the switch to application mode. Reading |
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| | | | | | | returns 0 if device is in firmware mode, 0xffffffff if in app mode. |
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| `LED` | r/w | r/w | 1B | u8 | | Control of the color LEDs in RBG LED on the board. |
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| | | | | | | Bit 0 is Blue, bit 1 is Green, and bit 2 is Red LED. |
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| `GPIO` | r/w | r/w | 1B | u8 | | Bits 0 and 1 contain the input level of GPIO 1 and 2. |
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| | | | | u8 | | Bits 3 and 4 store the output level of GPIO 3 and 4. |
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| `APP_ADDR` | r/w | r | 4B | u32 | | Firmware stores app load address here, so app can read its own location |
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| `APP_SIZE` | r/w | r | 4B | u32 | | Firmware stores app app size here, so app can read its own size |
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| `BLAKE2S` | r/w | r | 4B | u32 | | Function pointer to a BLAKE2S function in the firmware |
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| `CDI_FIRST` | r/w | r | 32B | u8[32] | | Compound Device Identifier (CDI). UDS+measurement... |
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| `CDI_LAST` | | r | | | | Last word of CDI |
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| `RAM_ASLR` | w | invisible | 4B | u32 | | Address Space Randomization seed value for the RAM |
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| `RAM_SCRAMBLE` | w | invisible | 4B | u32 | | Data scrambling seed value for the RAM |
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| `CPU_MON_CTRL` | w | w | 4B | u32 | | Bit 0 enables CPU execution monitor. Can't be unset. Lock adresses |
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| `CPU_MON_FIRST` | w | w | 4B | u32 | | First address of the area monitored for execution attempts |
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| `CPU_MON_LAST` | w | w | 4B | u32 | | Last address of the area monitored for execution attempts |
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[^3]: The UDS can only be read *once* per power-cycle.
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