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Add incoming and outgoing CTS (Clear To Send) signals for the FPGA

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to let the CH552 and FPGA signal each other that it is OK to send
UART data. The CTS signals indicate "OK to send" if high. If an
incoming CTS signal goes low, the receiver of that signal should
immediatly stop sending UART data.
This commit is contained in:
Jonas Thörnblad 2024-12-17 17:18:45 +01:00
parent 0213d64039
commit aaec7bbc3e
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GPG key ID: 2D318AD00A326F95
7 changed files with 54 additions and 5 deletions
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hw/application_fpga/tb/application_fpga_verilator.cc
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@ -315,6 +315,7 @@ int main(int argc, char **argv, char **env)
uart_init(&u, &top.interface_tx, &top.interface_rx, BIT_DIV);
top.clk = 0;
top.interface_ch552_cts = 1;
while (!Verilated::gotFinish()) {
uint8_t to_host = 0;