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Fix bit bit width mismatches

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Joachim Strömbergson 2022-10-12 10:21:50 +02:00
parent f75860c2a2
commit a9fd26da3b
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GPG Key ID: 865B8A548EA61679
1 changed files with 4 additions and 4 deletions
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8
hw/application_fpga/core/trng/rtl/rosc.v
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@ -51,8 +51,8 @@ module rosc(
//---------------------------------------------------------------- //----------------------------------------------------------------
// Registers with associated wires. // Registers with associated wires.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg [16 : 0] cycle_ctr_reg; reg [15 : 0] cycle_ctr_reg;
reg [16 : 0] cycle_ctr_new; reg [15 : 0] cycle_ctr_new;
reg cycle_ctr_done; reg cycle_ctr_done;
reg cycle_ctr_rst; reg cycle_ctr_rst;
@ -223,7 +223,7 @@ module rosc(
cycle_ctr_new = cycle_ctr_reg + 1'h1; cycle_ctr_new = cycle_ctr_reg + 1'h1;
if (cycle_ctr_rst) begin if (cycle_ctr_rst) begin
cycle_ctr_new = 24'h0; cycle_ctr_new = 16'h0;
end end
if (cycle_ctr_reg == SAMPLE_RATE) begin if (cycle_ctr_reg == SAMPLE_RATE) begin
@ -247,7 +247,7 @@ module rosc(
cycle_ctr_rst = 1'h0; cycle_ctr_rst = 1'h0;
data_ready_set = 1'h0; data_ready_set = 1'h0;
entropy_we = 1'h0; entropy_we = 1'h0;
bit_ctr_new = 6'h0; bit_ctr_new = 5'h0;
bit_ctr_we = 1'h0; bit_ctr_we = 1'h0;
rosc_ctrl_new = CTRL_SAMPLE1; rosc_ctrl_new = CTRL_SAMPLE1;
rosc_ctrl_we = 1'h0; rosc_ctrl_we = 1'h0;