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Add fw_ram module

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Joachim Strömbergson 2022-10-11 16:58:26 +02:00
parent 7e0692b150
commit a51619e5b7
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GPG key ID: 865B8A548EA61679
4 changed files with 132 additions and 2 deletions
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5
hw/application_fpga/Makefile
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@ -42,11 +42,11 @@ ASFLAGS = -target riscv32-unknown-none-elf -march=rv32imc -mabi=ilp32 -mno-relax
ICE40_SIM_CELLS = $(shell yosys-config --datdir/ice40/cells_sim.v)
# FPGA specific Verilog source files.
# FPGA specific source files.
FPGA_SRC = $(P)/rtl/application_fpga.v \
$(P)/rtl/clk_reset_gen.v
# Verilator simulation specific Verilog source files.
# Verilator simulation specific source files.
VERILATOR_FPGA_SRC = $(P)/tb/application_fpga_vsim.v \
$(P)/tb/reset_gen_vsim.v
@ -54,6 +54,7 @@ VERILATOR_FPGA_SRC = $(P)/tb/application_fpga_vsim.v \
VERILOG_SRCS = \
$(P)/rtl/ram.v \
$(P)/rtl/rom.v \
$(P)/rtl/fw_ram.v \
$(P)/core/picorv32/rtl/picorv32.v \
$(P)/core/timer/rtl/timer_core.v \
$(P)/core/timer/rtl/timer.v \