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Add Winbond flash memory model. Added note about the model

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in the README.
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Joachim Strömbergson 2024-01-31 09:02:34 +01:00
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hw/application_fpga/core/tk1/README.md
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@ -175,4 +175,29 @@ execution is possible.
The core is implemented as a single module. Future versions will
probably be separated into separate modules.
## Winbond Flash memory model
The testbench for the SPI master includes a memory model of the Flash
memory. The model is provided by Winbond and the copyright for the
model is:
```
/******************************************************************************
Winbond Electronics Corporation
Verilog Simulation for W25Q80DL Serial Flash Memory
V1.01
Copyright (c) 2001-2015 Winbond Electronics Corporation
All Rights Reserved.
Notes:
Versions:
12/09/2015 Initial Version
******************************************************************************/
```
---

1981
hw/application_fpga/core/tk1/tb/W25Q80DL.v Normal file
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