make a spifw to test spi access from fw

hw/application_fpga/Makefile

@@ -107,6 +107,16 @@ TESTFW_OBJS = \
 	$(P)/fw/tk1/lib.o \
 	$(P)/fw/tk1/blake2s/blake2s.o
 
+SPIFW_OBJS = \
+	$(P)/fw/spifw/main.o \
+	$(P)/fw/spifw/start.o \
+	$(P)/fw/spifw/spi.o \
+	$(P)/fw/spifw/flash.o \
+	$(P)/fw/tk1/proto.o \
+	$(P)/fw/tk1/lib.o \
+	$(P)/fw/tk1/assert.o \
+	$(P)/fw/tk1/led.o
+
 #-------------------------------------------------------------------
 # All: Complete build of HW and FW.
 #-------------------------------------------------------------------
@@ -143,6 +153,7 @@ LDFLAGS=-T $(P)/fw/tk1/firmware.lds
 
 $(FIRMWARE_OBJS): $(FIRMWARE_DEPS)
 $(TESTFW_OBJS): $(FIRMWARE_DEPS)
+$(SPIFW_OBJS): $(FIRMWARE_DEPS)
 
 firmware.elf: $(FIRMWARE_OBJS) $(P)/fw/tk1/firmware.lds
 	$(CC) $(CFLAGS) $(FIRMWARE_OBJS) $(LDFLAGS) -o $@
@@ -158,6 +169,9 @@ splint:
 testfw.elf: $(TESTFW_OBJS) $(P)/fw/tk1/firmware.lds
 	$(CC) $(CFLAGS) $(TESTFW_OBJS) $(LDFLAGS) -o $@
 
+spifw.elf: $(SPIFW_OBJS) $(P)/fw/tk1/firmware.lds
+	$(CC) $(CFLAGS) $(SPIFW_OBJS) $(LDFLAGS) -o $@
+
 # Generate a fake BRAM file that will be filled in later after place-n-route
 bram_fw.hex:
 	$(ICESTORM_PATH)icebram -v -g 32 $(BRAM_FW_SIZE) > $@
@@ -166,6 +180,8 @@ firmware.hex: firmware.bin firmware_size_mismatch
 	python3 $(P)/tools/makehex/makehex.py $< $(BRAM_FW_SIZE) > $@
 testfw.hex: testfw.bin testfw_size_mismatch
 	python3 $(P)/tools/makehex/makehex.py $< $(BRAM_FW_SIZE) > $@
+spifw.hex: spifw.bin testfw_size_mismatch
+	python3 $(P)/tools/makehex/makehex.py $< $(BRAM_FW_SIZE) > $@
 
 .PHONY: check-binary-hashes
 check-binary-hashes:
@@ -273,6 +289,10 @@ application_fpga_testfw.bin: application_fpga.asc bram_fw.hex testfw.hex
 	$(ICESTORM_PATH)icepack $<.tmp $@
 	@-$(RM) $<.tmp
 
+application_fpga_spifw.bin: application_fpga.asc bram_fw.hex spifw.hex
+	$(ICESTORM_PATH)icebram -v bram_fw.hex spifw.hex < $< > $<.tmp
+	$(ICESTORM_PATH)icepack $<.tmp $@
+	@-$(RM) $<.tmp
 #-------------------------------------------------------------------
 # post-synthesis functional simulation.
 #-------------------------------------------------------------------

hw/application_fpga/fw/spifw/flash.c

@@ -0,0 +1,193 @@
+// Copyright (C) 2022, 2023 - Tillitis AB
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "flash.h"
+#include "../tk1/types.h"
+#include "spi.h"
+#include <stdbool.h>
+// #include <stddef.h>
+// #include <stdint.h>
+
+#include "../tk1_mem.h"
+
+// clang-format off
+static volatile uint32_t *timer		        = (volatile uint32_t *)TK1_MMIO_TIMER_TIMER;
+static volatile uint32_t *timer_prescaler	= (volatile uint32_t *)TK1_MMIO_TIMER_PRESCALER;
+static volatile uint32_t *timer_status		= (volatile uint32_t *)TK1_MMIO_TIMER_STATUS;
+static volatile uint32_t *timer_ctrl		= (volatile uint32_t *)TK1_MMIO_TIMER_CTRL;
+// clang-format on
+
+// CPU clock frequency in Hz
+#define CPUFREQ 18000000
+
+static void delay(int timeout_ms)
+{
+	// Tick once every centisecond
+	*timer_prescaler = CPUFREQ / 100;
+	*timer = timeout_ms / 10;
+
+	*timer_ctrl |= (1 << TK1_MMIO_TIMER_CTRL_START_BIT);
+
+	while (*timer_status != 0) {
+	}
+
+	// Stop timer
+	*timer_ctrl |= (1 << TK1_MMIO_TIMER_CTRL_STOP_BIT);
+}
+
+bool flash_is_busy()
+{
+	uint8_t tx_buf = READ_STATUS_REG_1;
+	uint8_t rx_buf = {0x00};
+
+	spi_transfer(&tx_buf, sizeof(tx_buf), &rx_buf, sizeof(rx_buf));
+
+	if (rx_buf & (1 << STATUS_REG_BUSY_BIT)) {
+		return true;
+	}
+
+	return false;
+}
+
+// Blocking until !busy
+void flash_wait_busy()
+{
+	while (flash_is_busy()) {
+		delay(10);
+	}
+}
+
+void flash_write_enable()
+{
+	uint8_t tx_buf = WRITE_ENABLE;
+
+	spi_write(&tx_buf, sizeof(tx_buf), NULL, 0);
+}
+
+void flash_write_disable()
+{
+	uint8_t tx_buf = WRITE_DISABLE;
+
+	spi_write(&tx_buf, sizeof(tx_buf), NULL, 0);
+}
+
+void flash_sector_erase(uint32_t address)
+{
+	uint8_t tx_buf[4] = {0x00};
+	tx_buf[0] = SECTOR_ERASE;
+	tx_buf[1] = (address >> ADDR_BYTE_3_BIT) & 0xFF;
+	tx_buf[2] = (address >> ADDR_BYTE_2_BIT) & 0xFF;
+	tx_buf[3] = (address >> ADDR_BYTE_1_BIT) & 0xFF;
+
+	flash_write_enable();
+	spi_write(tx_buf, sizeof(tx_buf), NULL, 0);
+	flash_wait_busy();
+}
+
+void flash_block_32_erase(uint32_t address)
+{
+	uint8_t tx_buf[4] = {0x00};
+	tx_buf[0] = BLOCK_ERASE_32K;
+	tx_buf[1] = (address >> ADDR_BYTE_3_BIT) & 0xFF;
+	tx_buf[2] = (address >> ADDR_BYTE_2_BIT) & 0xFF;
+	tx_buf[3] = (address >> ADDR_BYTE_1_BIT) & 0xFF;
+
+	flash_write_enable();
+	spi_write(tx_buf, sizeof(tx_buf), NULL, 0);
+	flash_wait_busy();
+}
+
+void flash_block_64_erase(uint32_t address)
+{
+	uint8_t tx_buf[4] = {0x00};
+	tx_buf[0] = BLOCK_ERASE_64K;
+	tx_buf[1] = (address >> ADDR_BYTE_3_BIT) & 0xFF;
+	tx_buf[2] = (address >> ADDR_BYTE_2_BIT) & 0xFF;
+	tx_buf[3] = (address >> ADDR_BYTE_1_BIT) & 0xFF;
+
+	flash_write_enable();
+	spi_write(tx_buf, sizeof(tx_buf), NULL, 0);
+	flash_wait_busy();
+}
+
+void flash_release_powerdown()
+{
+	uint8_t tx_buf[4] = {0x00};
+	tx_buf[0] = RELEASE_POWER_DOWN;
+
+	spi_write(tx_buf, sizeof(tx_buf), NULL, 0);
+}
+
+void flash_powerdown()
+{
+	uint8_t tx_buf = POWER_DOWN;
+
+	spi_write(&tx_buf, sizeof(tx_buf), NULL, 0);
+}
+
+void flash_read_manufacturer_device_id(uint8_t *device_id)
+{
+	uint8_t tx_buf[4] = {0x00};
+	tx_buf[0] = READ_MANUFACTURER_ID;
+
+	spi_transfer(tx_buf, sizeof(tx_buf), device_id, 2);
+}
+
+void flash_read_jedec_id(uint8_t *jedec_id)
+{
+	uint8_t tx_buf = READ_JEDEC_ID;
+
+	spi_transfer(&tx_buf, sizeof(tx_buf), jedec_id, 3);
+}
+
+void flash_read_unique_id(uint8_t *unique_id)
+{
+	uint8_t tx_buf[5] = {0x00};
+	tx_buf[0] = READ_UNIQUE_ID;
+
+	spi_transfer(tx_buf, sizeof(tx_buf), unique_id, 8);
+}
+
+void flash_read_status(uint8_t *status_reg)
+{
+	uint8_t tx_buf = READ_STATUS_REG_1;
+
+	spi_transfer(&tx_buf, sizeof(tx_buf), status_reg, 1);
+
+	tx_buf = READ_STATUS_REG_2;
+	spi_transfer(&tx_buf, sizeof(tx_buf), status_reg + 1, 1);
+}
+
+int flash_read_data(uint32_t address, uint8_t *dest_buf, size_t size)
+{
+	uint8_t tx_buf[4] = {0x00};
+	tx_buf[0] = READ_DATA;
+	tx_buf[1] = (address >> ADDR_BYTE_3_BIT) & 0xFF;
+	tx_buf[2] = (address >> ADDR_BYTE_2_BIT) & 0xFF;
+	tx_buf[3] = (address >> ADDR_BYTE_1_BIT) & 0xFF;
+
+	return spi_transfer(tx_buf, sizeof(tx_buf), dest_buf, size);
+}
+
+int flash_write_data(uint32_t address, uint8_t *data, size_t size)
+{
+	if (size <= 0 || size > 256) {
+		return -1;
+	}
+
+	uint8_t tx_buf[4] = {0x00};
+	tx_buf[0] = PAGE_PROGRAM;
+	tx_buf[1] = (address >> ADDR_BYTE_3_BIT) & 0xFF;
+	tx_buf[2] = (address >> ADDR_BYTE_2_BIT) & 0xFF;
+	tx_buf[3] = (address >> ADDR_BYTE_1_BIT) & 0xFF;
+
+	flash_write_enable();
+
+	if (spi_write(tx_buf, sizeof(tx_buf), data, size) != 0) {
+		return -1;
+	} else {
+		flash_wait_busy();
+	}
+
+	return 0;
+}

hw/application_fpga/fw/spifw/flash.h

@@ -0,0 +1,59 @@
+// Copyright (C) 2022, 2023 - Tillitis AB
+// SPDX-License-Identifier: GPL-2.0-only
+
+#ifndef TKEY_FLASH_H
+#define TKEY_FLASH_H
+
+#include <stdbool.h>
+#include "../tk1/types.h"
+// #include <stddef.h>
+// #include <stdint.h>
+
+#define WRITE_ENABLE 0x06
+#define WRITE_DISABLE 0x04
+
+#define READ_STATUS_REG_1 0x05
+#define READ_STATUS_REG_2 0x35
+#define WRITE_STATUS_REG 0x01
+
+#define PAGE_PROGRAM 0x02
+#define SECTOR_ERASE 0x20
+#define BLOCK_ERASE_32K 0x52
+#define BLOCK_ERASE_64K 0xD8
+#define CHIP_ERASE 0xC7
+
+#define POWER_DOWN 0xB9
+#define READ_DATA 0x03
+#define RELEASE_POWER_DOWN 0xAB
+
+#define READ_MANUFACTURER_ID 0x90
+#define READ_JEDEC_ID 0x9F
+#define READ_UNIQUE_ID 0x4B
+
+#define ENABLE_RESET 0x66
+#define RESET 0x99
+
+#define ADDR_BYTE_3_BIT 16
+#define ADDR_BYTE_2_BIT 8
+#define ADDR_BYTE_1_BIT 0
+
+#define STATUS_REG_BUSY_BIT 0
+#define STATUS_REG_WEL_BIT 1
+
+bool flash_is_busy(void);
+void flash_wait_busy(void);
+void flash_write_enable(void);
+void flash_write_disable(void);
+void flash_sector_erase(uint32_t address);
+void flash_block_32_erase(uint32_t address);
+void flash_block_64_erase(uint32_t address);
+void flash_release_powerdown(void);
+void flash_powerdown(void);
+void flash_read_manufacturer_device_id(uint8_t *device_id);
+void flash_read_jedec_id(uint8_t *jedec_id);
+void flash_read_unique_id(uint8_t *unique_id);
+void flash_read_status(uint8_t *status_reg);
+int flash_read_data(uint32_t address, uint8_t *dest_buf, size_t size);
+int flash_write_data(uint32_t address, uint8_t *data, size_t size);
+
+#endif

hw/application_fpga/fw/spifw/main.c

@@ -0,0 +1,171 @@
+// Copyright (C) 2022, 2023 - Tillitis AB
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "../tk1/assert.h"
+#include "../tk1/led.h"
+#include "../tk1/lib.h"
+#include "../tk1/proto.h"
+#include "../tk1_mem.h"
+// #include <stdbool.h>
+// #include <stdint.h>
+// #include <tkey/touch.h>
+#include "../tk1/types.h"
+
+#include "flash.h"
+#include "spi.h"
+
+// clang-format off
+static volatile uint32_t *trng_status     = (volatile uint32_t *)TK1_MMIO_TRNG_STATUS;
+static volatile uint32_t *trng_entropy    = (volatile uint32_t *)TK1_MMIO_TRNG_ENTROPY;
+// clang-format on
+
+static uint8_t rnd_byte(void)
+{
+	while ((*trng_status & (1 << TK1_MMIO_TRNG_STATUS_READY_BIT)) == 0) {
+	}
+	return (*trng_entropy & 0xff);
+}
+
+//------------------------------------------------------------------
+// dump_memory
+// dump the complete contents of the memory
+//------------------------------------------------------------------
+void spi_dump_memory(void)
+{
+	flash_release_powerdown();
+
+	uint8_t rx_buf[4096] = {0x00};
+
+	for (int block = 0; block < 0x02; block += 1) {
+		uint32_t address = 0x00000000;
+		address |= (block << ADDR_BYTE_3_BIT) & 0x00FF0000;
+		for (int i = 0; i < 16; i++) {
+			memset(rx_buf, 0x00, sizeof(rx_buf));
+			flash_read_data(address, rx_buf, sizeof(rx_buf));
+			write(rx_buf, sizeof(rx_buf));
+			address += 4096;
+		}
+	}
+}
+
+bool comp(uint8_t *a, uint8_t b, size_t size)
+{
+	for (size_t i = 0; i < size; i++) {
+		if (a[i] != b) {
+			return false;
+		}
+	}
+	return true;
+}
+
+//------------------------------------------------------------------
+// Test sequence.
+// Green LED = OK, Red LED = NOK.
+// It is fail fast, so any failed test gives an instant RED LED.
+//
+// * Check if the SPI Master exists by reading if it is ready.
+// * Wait for touch to start test (blue flash).
+// * Read IDs and print to serial port.
+// * Erase area (address: 0x00080000).
+// * Read area, compare to 0xFF.
+// * Write known pattern of a random byte.
+// * Read area, compare to pattern.
+// * Write known pattern of a random byte to another page.
+// * Read area, compare to pattern.
+// * If successful, LED Green.
+// * Wait for touch to dump beginning of flash (bitstream)
+
+//* one can use for example vimdiff <(xxd output.bin) <(xxd
+// application_fpga.bin)
+
+//------------------------------------------------------------------
+int main(void)
+{
+	// Check if the SPI master exists on the hardware.
+	// Since this is directly in main, the SPI master should
+	// be ready, otherwise we can assume it does not exists in
+	// the FGPA.
+	if (!spi_ready()) {
+		assert(1 == 2);
+	}
+
+	// Wait for terminal program and a character to be typed
+	readbyte();
+
+	uint8_t read_buf[0xff] = {0x00};
+
+	// touch_wait(LED_BLUE, 0); // start test
+	flash_release_powerdown();
+
+	// Read out IDs
+	flash_read_manufacturer_device_id(read_buf);
+	write(read_buf, 2);
+
+	memset(read_buf, 0x00, sizeof(read_buf));
+	flash_read_unique_id(read_buf);
+	write(read_buf, 8);
+
+	memset(read_buf, 0x00, sizeof(read_buf));
+	flash_read_jedec_id(read_buf);
+	write(read_buf, 3);
+
+	// Erase area
+	uint32_t start_address = 0x00080000;
+
+	set_led(LED_RED);
+	flash_sector_erase(start_address); // block 8
+	set_led(LED_BLUE);
+
+	// Read area, compare to 0xFF
+	memset(read_buf, 0x00, sizeof(read_buf));
+	flash_read_data(start_address, read_buf, 0xff);
+	write(read_buf, sizeof(read_buf));
+
+	if (!comp(read_buf, 0xff, sizeof(read_buf))) {
+		set_led(LED_RED);
+		assert(1 == 2);
+	}
+
+	// Write a known pattern of a random byte
+	uint8_t write_buf[255] = {0x00};
+	uint8_t byte = rnd_byte();
+	memset(write_buf, byte, sizeof(write_buf));
+
+	flash_write_data(start_address, write_buf, sizeof(write_buf));
+
+	// Read area, compare to pattern
+	memset(read_buf, 0x00, sizeof(read_buf));
+	flash_read_data(start_address, read_buf, 0xff);
+	write(read_buf, sizeof(read_buf));
+
+	if (!comp(read_buf, byte, sizeof(read_buf))) {
+		set_led(LED_RED);
+		assert(1 == 2);
+	}
+
+	// Write a known pattern of a random byte
+	start_address += 0x100; // next page
+
+	byte = rnd_byte();
+	memset(write_buf, byte, sizeof(write_buf));
+	flash_write_data(start_address, write_buf, sizeof(write_buf));
+
+	// Read area, compare to pattern
+	memset(read_buf, 0x00, sizeof(read_buf));
+	flash_read_data(start_address, read_buf, 0xff);
+	write(read_buf, sizeof(read_buf));
+
+	if (!comp(read_buf, byte, sizeof(read_buf))) {
+		set_led(LED_RED);
+		assert(1 == 2);
+	}
+
+	// It this is reached, the read/writing is successful.
+	// touch_wait(LED_GREEN, 0); // start dump
+	set_led(LED_BLACK);
+	spi_dump_memory();
+
+	for (;;) {
+		set_led(LED_GREEN);
+	}
+}

hw/application_fpga/fw/spifw/spi.c

@@ -0,0 +1,104 @@
+// Copyright (C) 2022, 2023 - Tillitis AB
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "spi.h"
+// #include <stddef.h>
+// #include <stdint.h>
+#include "../tk1/types.h"
+#include "../tk1_mem.h"
+
+// clang-format off
+static volatile uint32_t *spi_en =         (volatile uint32_t *)(TK1_MMIO_TK1_BASE | 0x200);
+static volatile uint32_t *spi_xfer =       (volatile uint32_t *)(TK1_MMIO_TK1_BASE | 0x204);
+static volatile uint32_t *spi_data =       (volatile uint32_t *)(TK1_MMIO_TK1_BASE | 0x208);
+// clang-format on
+
+// returns non-zero when the SPI-master is ready, and zero if not
+// ready. This can be used to check if the SPI-master is available
+// in the hardware.
+int spi_ready()
+{
+	return *spi_xfer;
+}
+
+static void spi_enable()
+{
+	*spi_en = 1;
+}
+
+static void spi_disable()
+{
+	*spi_en = 0;
+}
+
+static void _spi_write(uint8_t *cmd, size_t size)
+{
+	for (int i = 0; i < size; i++) {
+		while (!spi_ready()) {
+		}
+
+		*spi_data = cmd[i];
+		*spi_xfer = 1;
+	}
+
+	while (!spi_ready()) {
+	}
+}
+
+static void _spi_read(uint8_t *buf, size_t size)
+{
+
+	while (!spi_ready()) {
+	}
+
+	for (int i = 0; i < size; i++) {
+
+		*spi_data = 0x00;
+		*spi_xfer = 1;
+
+		// wait until spi master is done
+		while (!spi_ready()) {
+		}
+
+		buf[i] = (*spi_data & 0xff);
+	}
+}
+
+int spi_write(uint8_t *cmd, size_t cmd_size, uint8_t *data, size_t data_size)
+{
+	if (cmd == NULL || cmd_size == 0) {
+		return -1;
+	}
+
+	spi_enable();
+
+	_spi_write(cmd, cmd_size);
+
+	if (data != NULL && data_size != 0) {
+		_spi_write(data, data_size);
+	}
+
+	spi_disable();
+
+	return 0;
+}
+
+int spi_transfer(uint8_t *tx_buf, size_t tx_size, uint8_t *rx_buf,
+		 size_t rx_size)
+{
+	if (tx_buf == NULL || tx_size == 0) {
+		return -1;
+	}
+
+	spi_enable();
+
+	_spi_write(tx_buf, tx_size);
+
+	if (rx_buf != NULL && rx_size != 0) {
+		_spi_read(rx_buf, rx_size);
+	}
+
+	spi_disable();
+
+	return 0;
+}

hw/application_fpga/fw/spifw/spi.h

@@ -0,0 +1,16 @@
+// Copyright (C) 2022, 2023 - Tillitis AB
+// SPDX-License-Identifier: GPL-2.0-only
+
+#ifndef TKEY_SPI_H
+#define TKEY_SPI_H
+
+// #include <stddef.h>
+// #include <stdint.h>
+#include "../tk1/types.h"
+
+int spi_ready(void);
+int spi_write(uint8_t *cmd, size_t size_cmd, uint8_t *data, size_t size_data);
+int spi_transfer(uint8_t *tx_buf, size_t tx_size, uint8_t *rx_buf,
+		 size_t rx_size);
+
+#endif

hw/application_fpga/fw/spifw/start.S

@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2022, 2023 - Tillitis AB
+ * SPDX-License-Identifier: GPL-2.0-only
+*/
+
+	.section ".text.init"
+	.globl _start
+_start:
+	li x1, 0
+	li x2, 0
+	li x3, 0
+	li x4, 0
+	li x5, 0
+	li x6, 0
+	li x7, 0
+	li x8, 0
+	li x9, 0
+	li x10,0
+	li x11,0
+	li x12,0
+	li x13,0
+	li x14,0
+	li x15,0
+	li x16,0
+	li x17,0
+	li x18,0
+	li x19,0
+	li x20,0
+	li x21,0
+	li x22,0
+	li x23,0
+	li x24,0
+	li x25,0
+	li x26,0
+	li x27,0
+	li x28,0
+	li x29,0
+	li x30,0
+	li x31,0
+
+	/* Clear all RAM */
+	li a0, 0x40000000 // TK1_RAM_BASE
+	li a1, 0x40020000 // TK1_RAM_BASE + TK1_RAM_SIZE
+clear:
+	sw zero, 0(a0)
+	addi a0, a0, 4
+	blt a0, a1, clear
+
+        /*
+         * For testfw we init stack at top of RAM
+         */
+        li sp, 0x40020000 // TK1_RAM_BASE + TK1_RAM_SIZE
+
+	call main
+
+loop:
+	j loop

hw/application_fpga/fw/tk1/proto.c

@@ -21,7 +21,7 @@ static volatile uint32_t *tx =     (volatile uint32_t *)TK1_MMIO_UART_TX_DATA;
 static uint8_t genhdr(uint8_t id, uint8_t endpoint, uint8_t status,
 		      enum cmdlen len);
 static int parseframe(uint8_t b, struct frame_header *hdr);
-static void write(uint8_t *buf, size_t nbytes);
+void write(uint8_t *buf, size_t nbytes);
 static int read(uint8_t *buf, size_t bufsize, size_t nbytes);
 static int bytelen(enum cmdlen cmdlen);
 
@@ -135,7 +135,7 @@ void writebyte(uint8_t b)
 	}
 }
 
-static void write(uint8_t *buf, size_t nbytes)
+void write(uint8_t *buf, size_t nbytes)
 {
 	for (int i = 0; i < nbytes; i++) {
 		writebyte(buf[i]);

hw/application_fpga/fw/tk1/proto.h

@@ -51,6 +51,7 @@ struct frame_header {
 };
 
 /*@ -exportlocal @*/
+void write(uint8_t *buf, size_t nbytes);
 void writebyte(uint8_t b);
 uint8_t readbyte(void);
 void fwreply(struct frame_header hdr, enum fwcmd rspcode, uint8_t *buf);