From 9ce2b8a84a3bf739a9c149208e827b22869a4d72 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Mon, 2 Jan 2023 13:10:40 +0100 Subject: [PATCH] Only accept tx data when the core is ready MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Joachim Strömbergson --- hw/application_fpga/core/uart/rtl/uart.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/application_fpga/core/uart/rtl/uart.v b/hw/application_fpga/core/uart/rtl/uart.v index 480ba37..482dc0b 100644 --- a/hw/application_fpga/core/uart/rtl/uart.v +++ b/hw/application_fpga/core/uart/rtl/uart.v @@ -238,7 +238,9 @@ module uart( end ADDR_TX_DATA: begin - core_txd_syn = 1'h1; + if (core_txd_ready) begin + core_txd_syn = 1'h1; + end end default: begin