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fpga/fw: Rename system_mode to app_mode

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Rename `system_mode` to `app_mode` as to not confuse it with syscall or
firmware mode. When `app_mode` is `1`/`true` we are in app mode.
This commit is contained in:
Mikael Ågren 2025-02-19 19:40:35 +01:00
parent 19ae709c81
commit 97de5e68fd
No known key found for this signature in database
GPG key ID: E02DA3D397792C46
14 changed files with 84 additions and 84 deletions
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4
hw/application_fpga/core/fw_ram/README.md
View file

@ -21,6 +21,6 @@ The contents of the fw_ram is cleared when the FPGA is powered up and
configured by the bitstream. The contents is not cleared by a system
reset.
If the system_mode input is set, i.e. in app mode, no memory
accesses are allowed. Any reads when the system_mode is set will
If the app_mode input is set, i.e. in app mode, no memory
accesses are allowed. Any reads when the app_mode is set will
return an all zero word.

44
hw/application_fpga/core/fw_ram/rtl/fw_ram.v
View file

@ -17,7 +17,7 @@ module fw_ram (
input wire clk,
input wire reset_n,
input wire system_mode,
input wire app_mode,
input wire cs,
input wire [ 3 : 0] we,
@ -37,7 +37,7 @@ module fw_ram (
reg [31 : 0] mem_read_data2;
reg [31 : 0] mem_read_data3;
reg ready_reg;
wire system_mode_cs;
wire app_mode_cs;
reg bank0;
reg bank1;
reg bank2;
@ -47,9 +47,9 @@ module fw_ram (
//----------------------------------------------------------------
// Concurrent assignment of ports.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
assign ready = ready_reg;
assign system_mode_cs = cs && ~system_mode;
assign read_data = tmp_read_data;
assign ready = ready_reg;
assign app_mode_cs = cs && ~app_mode;
//----------------------------------------------------------------
@ -77,12 +77,12 @@ module fw_ram (
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
.RCLKE(1'h1),
.RE(system_mode_cs & bank0),
.RE(app_mode_cs & bank0),
.WADDR({3'h0, address[7 : 0]}),
.WCLK(clk),
.WCLKE(1'h1),
.WDATA(write_data[15 : 0]),
.WE((|we & system_mode_cs & bank0)),
.WE((|we & app_mode_cs & bank0)),
.MASK({{8{~we[1]}}, {8{~we[0]}}})
);
@ -108,12 +108,12 @@ module fw_ram (
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
.RCLKE(1'h1),
.RE(system_mode_cs & bank0),
.RE(app_mode_cs & bank0),
.WADDR({3'h0, address[7 : 0]}),
.WCLK(clk),
.WCLKE(1'h1),
.WDATA(write_data[31 : 16]),
.WE((|we & system_mode_cs & bank0)),
.WE((|we & app_mode_cs & bank0)),
.MASK({{8{~we[3]}}, {8{~we[2]}}})
);
@ -139,12 +139,12 @@ module fw_ram (
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
.RCLKE(1'h1),
.RE(system_mode_cs & bank1),
.RE(app_mode_cs & bank1),
.WADDR({3'h0, address[7 : 0]}),
.WCLK(clk),
.WCLKE(1'h1),
.WDATA(write_data[15 : 0]),
.WE((|we & system_mode_cs & bank1)),
.WE((|we & app_mode_cs & bank1)),
.MASK({{8{~we[1]}}, {8{~we[0]}}})
);
@ -170,12 +170,12 @@ module fw_ram (
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
.RCLKE(1'h1),
.RE(system_mode_cs & bank1),
.RE(app_mode_cs & bank1),
.WADDR({3'h0, address[7 : 0]}),
.WCLK(clk),
.WCLKE(1'h1),
.WDATA(write_data[31 : 16]),
.WE((|we & system_mode_cs & bank1)),
.WE((|we & app_mode_cs & bank1)),
.MASK({{8{~we[3]}}, {8{~we[2]}}})
);
@ -201,12 +201,12 @@ module fw_ram (
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
.RCLKE(1'h1),
.RE(system_mode_cs & bank2),
.RE(app_mode_cs & bank2),
.WADDR({3'h0, address[7 : 0]}),
.WCLK(clk),
.WCLKE(1'h1),
.WDATA(write_data[15 : 0]),
.WE((|we & system_mode_cs & bank2)),
.WE((|we & app_mode_cs & bank2)),
.MASK({{8{~we[1]}}, {8{~we[0]}}})
);
@ -232,12 +232,12 @@ module fw_ram (
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
.RCLKE(1'h1),
.RE(system_mode_cs & bank2),
.RE(app_mode_cs & bank2),
.WADDR({3'h0, address[7 : 0]}),
.WCLK(clk),
.WCLKE(1'h1),
.WDATA(write_data[31 : 16]),
.WE((|we & system_mode_cs & bank2)),
.WE((|we & app_mode_cs & bank2)),
.MASK({{8{~we[3]}}, {8{~we[2]}}})
);
@ -263,12 +263,12 @@ module fw_ram (
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
.RCLKE(1'h1),
.RE(system_mode_cs & bank3),
.RE(app_mode_cs & bank3),
.WADDR({3'h0, address[7 : 0]}),
.WCLK(clk),
.WCLKE(1'h1),
.WDATA(write_data[15 : 0]),
.WE((|we & system_mode_cs & bank3)),
.WE((|we & app_mode_cs & bank3)),
.MASK({{8{~we[1]}}, {8{~we[0]}}})
);
@ -294,12 +294,12 @@ module fw_ram (
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
.RCLKE(1'h1),
.RE(system_mode_cs & bank3),
.RE(app_mode_cs & bank3),
.WADDR({3'h0, address[7 : 0]}),
.WCLK(clk),
.WCLKE(1'h1),
.WDATA(write_data[31 : 16]),
.WE((|we & system_mode_cs & bank3)),
.WE((|we & app_mode_cs & bank3)),
.MASK({{8{~we[3]}}, {8{~we[2]}}})
);
@ -326,7 +326,7 @@ module fw_ram (
bank3 = 1'h0;
tmp_read_data = 32'h0;
if (system_mode_cs) begin
if (app_mode_cs) begin
case (address[9:8])
2'b11: begin
bank3 = 1'h1;

12
hw/application_fpga/core/tk1/README.md
View file

@ -26,7 +26,7 @@ applications.
### Control of execution mode
```
ADDR_SYSTEM_MODE_CTRL: 0x08
ADDR_APP_MODE_CTRL: 0x08
```
This register controls if the device is executing in FW mode or in App
@ -75,7 +75,7 @@ ADDR_APP_SIZE: 0x0d
These registers provide read only information to the loaded app to
itself - where it was loaded and its size. The values are written by
FW as part of the loading of the app. The registers can't be written
when the `ADDR_SYSTEM_MODE_CTRL` has been set.
when the `ADDR_APP_MODE_CTRL` has been set.
### Access to Blake2s
@ -86,7 +86,7 @@ ADDR_BLAKE2S: 0x10
This register provides the 32-bit function pointer address to the
Blake2s hash function in the FW. It is written by FW during boot. The
register can't be written to when the `ADDR_SYSTEM_MODE_CTRL` has been
register can't be written to when the `ADDR_APP_MODE_CTRL` has been
set.
@ -100,9 +100,9 @@ ADDR_CDI_LAST: 0x27
These registers provide access to the 256-bit compound device secret
calculated by the FW as part of loading an application. The registers
are written by the FW. The register can't be written to when the
`ADDR_SYSTEM_MODE_CTRL` has been set. The CDI is readable by apps,
which can then use it as a base secret for any other secrets required
to carry out their intended use case.
`ADDR_APP_MODE_CTRL` has been set. The CDI is readable by apps, which
can then use it as a base secret for any other secrets required to
carry out their intended use case.
### Access to UDI

40
hw/application_fpga/core/tk1/rtl/tk1.v
View file

@ -20,7 +20,7 @@ module tk1 #(
input wire reset_n,
input wire cpu_trap,
output wire system_mode,
output wire app_mode,
input wire [31 : 0] cpu_addr,
input wire cpu_instr,
@ -63,7 +63,7 @@ module tk1 #(
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_SYSTEM_MODE_CTRL = 8'h08;
localparam ADDR_APP_MODE_CTRL = 8'h08;
localparam ADDR_LED = 8'h09;
localparam LED_R_BIT = 2;
@ -116,8 +116,8 @@ module tk1 #(
reg [31 : 0] cdi_mem [0 : 7];
reg cdi_mem_we;
reg system_mode_reg;
reg system_mode_we;
reg app_mode_reg;
reg app_mode_we;
reg [ 2 : 0] led_reg;
reg led_we;
@ -189,7 +189,7 @@ module tk1 #(
assign read_data = tmp_read_data;
assign ready = tmp_ready;
assign system_mode = system_mode_reg;
assign app_mode = app_mode_reg;
assign force_trap = force_trap_reg;
@ -252,7 +252,7 @@ module tk1 #(
//----------------------------------------------------------------
always @(posedge clk) begin : reg_update
if (!reset_n) begin
system_mode_reg <= 1'h0;
app_mode_reg <= 1'h0;
led_reg <= 3'h6;
gpio1_reg <= 2'h0;
gpio2_reg <= 2'h0;
@ -291,8 +291,8 @@ module tk1 #(
gpio2_reg[0] <= gpio2;
gpio2_reg[1] <= gpio2_reg[0];
if (system_mode_we) begin
system_mode_reg <= 1'h1;
if (app_mode_we) begin
app_mode_reg <= 1'h1;
end
if (led_we) begin
@ -489,7 +489,7 @@ module tk1 #(
// api
//----------------------------------------------------------------
always @* begin : api
system_mode_we = 1'h0;
app_mode_we = 1'h0;
led_we = 1'h0;
gpio3_we = 1'h0;
gpio4_we = 1'h0;
@ -516,8 +516,8 @@ module tk1 #(
if (cs) begin
tmp_ready = 1'h1;
if (we) begin
if (address == ADDR_SYSTEM_MODE_CTRL) begin
system_mode_we = 1'h1;
if (address == ADDR_APP_MODE_CTRL) begin
app_mode_we = 1'h1;
end
if (address == ADDR_LED) begin
@ -530,13 +530,13 @@ module tk1 #(
end
if (address == ADDR_APP_START) begin
if (!system_mode_reg) begin
if (!app_mode_reg) begin
app_start_we = 1'h1;
end
end
if (address == ADDR_APP_SIZE) begin
if (!system_mode_reg) begin
if (!app_mode_reg) begin
app_size_we = 1'h1;
end
end
@ -546,25 +546,25 @@ module tk1 #(
end
if (address == ADDR_BLAKE2S) begin
if (!system_mode_reg) begin
if (!app_mode_reg) begin
blake2s_addr_we = 1'h1;
end
end
if ((address >= ADDR_CDI_FIRST) && (address <= ADDR_CDI_LAST)) begin
if (!system_mode_reg) begin
if (!app_mode_reg) begin
cdi_mem_we = 1'h1;
end
end
if (address == ADDR_RAM_ADDR_RAND) begin
if (!system_mode_reg) begin
if (!app_mode_reg) begin
ram_addr_rand_we = 1'h1;
end
end
if (address == ADDR_RAM_DATA_RAND) begin
if (!system_mode_reg) begin
if (!app_mode_reg) begin
ram_data_rand_we = 1'h1;
end
end
@ -611,8 +611,8 @@ module tk1 #(
tmp_read_data = TK1_VERSION;
end
if (address == ADDR_SYSTEM_MODE_CTRL) begin
tmp_read_data = {32{system_mode_reg}};
if (address == ADDR_APP_MODE_CTRL) begin
tmp_read_data = {32{app_mode_reg}};
end
if (address == ADDR_LED) begin
@ -640,7 +640,7 @@ module tk1 #(
end
if ((address >= ADDR_UDI_FIRST) && (address <= ADDR_UDI_LAST)) begin
if (!system_mode_reg) begin
if (!app_mode_reg) begin
tmp_read_data = udi_rdata;
end
end

16
hw/application_fpga/core/tk1/tb/tb_tk1.v
View file

@ -27,7 +27,7 @@ module tb_tk1 ();
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_SYSTEM_MODE_CTRL = 8'h08;
localparam ADDR_APP_MODE_CTRL = 8'h08;
localparam ADDR_LED = 8'h09;
localparam LED_R_BIT = 2;
@ -76,7 +76,7 @@ module tb_tk1 ();
reg tb_clk;
reg tb_reset_n;
reg tb_cpu_trap;
wire tb_system_mode;
wire tb_app_mode;
reg [31 : 0] tb_cpu_addr;
reg tb_cpu_instr;
@ -122,7 +122,7 @@ module tb_tk1 ();
.reset_n(tb_reset_n),
.cpu_trap(tb_cpu_trap),
.system_mode(tb_system_mode),
.app_mode(tb_app_mode),
.cpu_addr (tb_cpu_addr),
.cpu_instr (tb_cpu_instr),
@ -192,7 +192,7 @@ module tb_tk1 ();
$display("------------");
if (tb_main_monitor) begin
$display("Inputs and outputs:");
$display("tb_cpu_trap: 0x%1x, system_mode: 0x%1x", tb_cpu_trap, tb_system_mode);
$display("tb_cpu_trap: 0x%1x, app_mode: 0x%1x", tb_cpu_trap, tb_app_mode);
$display("cpu_addr: 0x%08x, cpu_instr: 0x%1x, cpu_valid: 0x%1x, force_tap: 0x%1x",
tb_cpu_addr, tb_cpu_instr, tb_cpu_valid, tb_force_trap);
$display("ram_addr_rand: 0x%08x, ram_data_rand: 0x%08x", tb_ram_addr_rand,
@ -529,7 +529,7 @@ module tb_tk1 ();
read_check_word(ADDR_CDI_LAST + 0, 32'h70717273);
$display("--- test3: Switch to app mode.");
write_word(ADDR_SYSTEM_MODE_CTRL, 32'hdeadbeef);
write_word(ADDR_APP_MODE_CTRL, 32'hdeadbeef);
$display("--- test3: Try to write CDI again.");
write_word(ADDR_CDI_FIRST + 0, 32'hfffefdfc);
@ -577,7 +577,7 @@ module tb_tk1 ();
read_check_word(ADDR_BLAKE2S, 32'hcafebabe);
$display("--- test4: Switch to app mode.");
write_word(ADDR_SYSTEM_MODE_CTRL, 32'hf00ff00f);
write_word(ADDR_APP_MODE_CTRL, 32'hf00ff00f);
$display("--- test4: Write Blake2s entry point again.");
write_word(ADDR_BLAKE2S, 32'hdeadbeef);
@ -613,7 +613,7 @@ module tb_tk1 ();
read_check_word(ADDR_APP_SIZE, 32'h47114711);
$display("--- test5: Switch to app mode.");
write_word(ADDR_SYSTEM_MODE_CTRL, 32'hf000000);
write_word(ADDR_APP_MODE_CTRL, 32'hf000000);
$display("--- test5: Write app start address and size again.");
write_word(ADDR_APP_START, 32'hdeadbeef);
@ -652,7 +652,7 @@ module tb_tk1 ();
dut.ram_addr_rand, dut.ram_data_rand);
$display("--- test6: Switch to app mode.");
write_word(ADDR_SYSTEM_MODE_CTRL, 32'hf000000);
write_word(ADDR_APP_MODE_CTRL, 32'hf000000);
$display("--- test6: Write to ADDR_RAM_ADDR_RAND and ADDR_RAM_DATA_RAND again.");
write_word(ADDR_RAM_ADDR_RAND, 32'hdeadbeef);

2
hw/application_fpga/core/uds/README.md
View file

@ -6,7 +6,7 @@ Unique Device Secret core
This core store and protect the Unique Device Secret (UDS) asset. The
UDS can be accessed as eight separate 32-bit words. The words can only
be accessed as long as the system_mode input is low, implying that the
be accessed as long as the app_mode input is low, implying that the
CPU is executing the FW.
The UDS words can be accessed in any order, but a given word can only

4
hw/application_fpga/core/uds/rtl/uds.v
View file

@ -17,7 +17,7 @@ module uds (
input wire clk,
input wire reset_n,
input wire system_mode,
input wire app_mode,
input wire cs,
input wire [ 2 : 0] address,
@ -89,7 +89,7 @@ module uds (
if (cs) begin
tmp_ready = 1'h1;
if (!system_mode) begin
if (!app_mode) begin
if (uds_rd_reg[address[2 : 0]] == 1'h0) begin
uds_rd_we = 1'h1;
end

8
hw/application_fpga/core/uds/tb/tb_uds.v
View file

@ -37,7 +37,7 @@ module tb_uds ();
reg tb_clk;
reg tb_reset_n;
reg tb_system_mode;
reg tb_app_mode;
reg tb_cs;
reg [ 7 : 0] tb_address;
wire [31 : 0] tb_read_data;
@ -50,7 +50,7 @@ module tb_uds ();
.clk(tb_clk),
.reset_n(tb_reset_n),
.system_mode(tb_system_mode),
.app_mode(tb_app_mode),
.cs(tb_cs),
.address(tb_address),
@ -95,7 +95,7 @@ module tb_uds ();
$display("State of DUT at cycle: %08d", cycle_ctr);
$display("------------");
$display("Inputs and outputs:");
$display("system_mode: 0x%1x", tb_system_mode);
$display("app_mode: 0x%1x", tb_app_mode);
$display("cs: 0x%1x, address: 0x%02x, read_data: 0x%08x", tb_cs, tb_address, tb_read_data);
$display("");
@ -160,7 +160,7 @@ module tb_uds ();
tb_clk = 1'h0;
tb_reset_n = 1'h1;
tb_system_mode = 1'h0;
tb_app_mode = 1'h0;
tb_cs = 1'h0;
tb_address = 8'h0;
end