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Use PLL and global buffer to increas clock speed

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Joachim Strömbergson 2022-09-27 16:41:38 +02:00
parent 610522201b
commit 90a57c4948
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3 changed files with 49 additions and 23 deletions
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17
hw/application_fpga/rtl/application_fpga.v
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@ -139,24 +139,11 @@ module application_fpga(
wire fw_app_mode;
//----------------------------------------------------------------
// Concurrent assignments.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Module instantiations.
//----------------------------------------------------------------
// Use the FPGA internal High Frequency OSCillator as clock source.
// 00: 48MHz, 01: 24MHz, 10: 12MHz, 11: 6MHz
/* verilator lint_off PINMISSING */
SB_HFOSC #(.CLKHF_DIV("0b10")
) u_hfosc (.CLKHFPU(1'b1),.CLKHFEN(1'b1),.CLKHF(clk));
/* verilator lint_on PINMISSING */
reset_gen #(.RESET_CYCLES(200))
reset_gen_inst(.clk(clk), .rst_n(reset_n));
clk_reset_gen #(.RESET_CYCLES(200))
reset_gen_inst(.clk(clk), .rst_n(reset_n));
picorv32 #(