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Merge d620ab1a03 into 0454e023cd

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Joachim Strömbergson 2024-04-25 17:47:09 +02:00 committed by GitHub
commit 909dd0a5ed
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1 changed files with 15 additions and 5 deletions
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20
hw/application_fpga/core/tk1/rtl/tk1.v
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@ -144,6 +144,9 @@ module tk1(
reg force_trap_reg;
reg force_trap_set;
reg cdi_access_reg;
reg cdi_access_we;
//----------------------------------------------------------------
// Wires.
@ -233,6 +236,7 @@ module tk1(
ram_aslr_reg <= 15'h0;
ram_scramble_reg <= 32'h0;
force_trap_reg <= 1'h0;
cdi_access_reg <= 1'h1;
end
else begin
@ -303,6 +307,10 @@ module tk1(
if (force_trap_set) begin
force_trap_reg <= 1'h1;
end
if (cdi_access_we) begin
cdi_access_reg <= 1'h0;
end
end
end // reg_update
@ -383,7 +391,7 @@ module tk1(
app_size_we = 1'h0;
blake2s_addr_we = 1'h0;
cdi_mem_we = 1'h0;
cdi_mem_we = 1'h0;
cdi_access_we = 1'h0;
ram_aslr_we = 1'h0;
ram_scramble_we = 1'h0;
cpu_mon_en_we = 1'h0;
@ -427,10 +435,10 @@ module tk1(
end
end
if ((address >= ADDR_CDI_FIRST) && (address <= ADDR_CDI_LAST)) begin
if (!switch_app_reg) begin
cdi_mem_we = 1'h1;
end
if ((address >= ADDR_CDI_FIRST) && (address <= ADDR_CDI_LAST) & !switch_app_reg ) begin
cdi_mem_we = 1'h1;
end else begin
cdi_access_we = 1'h1;
end
if (address == ADDR_RAM_ASLR) begin
@ -501,7 +509,9 @@ module tk1(
end
if ((address >= ADDR_CDI_FIRST) && (address <= ADDR_CDI_LAST)) begin
if (cdi_access_reg) begin
tmp_read_data = cdi_mem[address[2 : 0]];
end
end
if ((address >= ADDR_UDI_FIRST) && (address <= ADDR_UDI_LAST)) begin