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Clarify access behaviour of the UDS

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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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Joachim Strömbergson 2023-03-28 10:02:57 +02:00
parent 688910bee4
commit 909b95cdaa
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3 changed files with 15 additions and 9 deletions
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11
doc/system_description/fpga.md
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@ -67,9 +67,14 @@ use the RAM during loading and measurement of the application.
Unique Device Secret memory. Unique Device Secret memory.
A 256 bit memory implemented using separate registers. The A 256 bit memory implemented using eight 32-bit registers. The
registers can only be accessed once between power cycling. registers can only be accessed once between power cycling. This means
Only the firmware can access the UDS memory core. that the UDS **must** be read as u32. If read as u8, only the first
byte from a given address will be correct, subsequent bytes will be
zero.
The UDS can only be read in FW mode. Reading from the UDS in APP mode
will return all zeros.
#### Application RAM #### Application RAM

7
doc/system_description/software.md
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@ -22,12 +22,13 @@ constrained environment, the application mode.
The firmware and application uses a memory mapped input/output (MMIO) The firmware and application uses a memory mapped input/output (MMIO)
for communication with the hardware. The memory map is constrained for communication with the hardware. The memory map is constrained
when running in application mode, e.g. UDS isn't readable, and the when running in application mode, e.g. FW-RAM and UDS isn't readable,
`APP_{ADDR, SIZE}` are not writable for the application. and several MMIO addresses are either not readable or not writable for
the application.
See table in the [System See table in the [System
Description](system_description.md#memory-mapped-hardware-functions) Description](system_description.md#memory-mapped-hardware-functions)
for details about the memory system and MMIO. for details about access rules control in the memory system and MMIO.
The firmware (and optionally all software) on the TKey can communicate The firmware (and optionally all software) on the TKey can communicate
to the host via the `UART_{RX,TX}_{STATUS,DATA}` registers, using the to the host via the `UART_{RX,TX}_{STATUS,DATA}` registers, using the

6
doc/system_description/system_description.md
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@ -242,15 +242,15 @@ Assigned core prefixes:
| `TIMER_STATUS` | r | r | | | | TIMER_STATUS_RUNNING_BIT is 1 when the timer is running. | | `TIMER_STATUS` | r | r | | | | TIMER_STATUS_RUNNING_BIT is 1 when the timer is running. |
| `TIMER_PRESCALER` | r/w | r/w | 4B | | | Prescaler init value. Write blocked when running. | | `TIMER_PRESCALER` | r/w | r/w | 4B | | | Prescaler init value. Write blocked when running. |
| `TIMER_TIMER` | r/w | r/w | 4B | | | Timer init or current value while running. Write blocked when running. | | `TIMER_TIMER` | r/w | r/w | 4B | | | Timer init or current value while running. Write blocked when running. |
| `UDS_FIRST` | r[^3] | invisible | 4B | u8[32] | | First word of Unique Device Secret key. | | `UDS_FIRST` | r[^3] | invisible | 4B | u8[32] | | First word of Unique Device Secret key. Note: Read once per power up. |
| `UDS_LAST` | | invisible | | | | The last word of the UDS | | `UDS_LAST` | | invisible | | | | The last word of the UDS. Note: Read once per power up. |
| `UART_BITRATE` | r/w | | | | | TBD | | `UART_BITRATE` | r/w | | | | | TBD |
| `UART_DATABITS` | r/w | | | | | TBD | | `UART_DATABITS` | r/w | | | | | TBD |
| `UART_STOPBITS` | r/w | | | | | TBD | | `UART_STOPBITS` | r/w | | | | | TBD |
| `UART_RX_STATUS` | r | r | 1B | u8 | | Non-zero when there is data to read | | `UART_RX_STATUS` | r | r | 1B | u8 | | Non-zero when there is data to read |
| `UART_RX_DATA` | r | r | 1B | u8 | | Data to read. Only LSB contains data | | `UART_RX_DATA` | r | r | 1B | u8 | | Data to read. Only LSB contains data |
| `UART_RX_BYTES` | r | r | 4B | u32 | | Number of bytes received from the host and not yet read by SW, FW. | | `UART_RX_BYTES` | r | r | 4B | u32 | | Number of bytes received from the host and not yet read by SW, FW. |
| `UART_TX_STATUS` | r | r | 1B | u8 | | Non-zero when it's OK to write data | | `UART_TX_STATUS` | r | r | 1B | u8 | | Non-zero when it's OK to write data to send. |
| `UART_TX_DATA` | w | w | 1B | u8 | | Data to send. Only LSB contains data | | `UART_TX_DATA` | w | w | 1B | u8 | | Data to send. Only LSB contains data |
| `TOUCH_STATUS` | r/w | r/w | | | | TOUCH_STATUS_EVENT_BIT is 1 when touched. After detecting a touch | | `TOUCH_STATUS` | r/w | r/w | | | | TOUCH_STATUS_EVENT_BIT is 1 when touched. After detecting a touch |
| | | | | | | event (reading a 1), write anything here to acknowledge it. | | | | | | | | event (reading a 1), write anything here to acknowledge it. |