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Debug fw_ram and add fw_app_mode access control

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Joachim Strömbergson 2022-10-13 13:14:10 +02:00
parent cbf1104fed
commit 8e493b6322
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GPG Key ID: 865B8A548EA61679
1 changed files with 28 additions and 10 deletions
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38
hw/application_fpga/rtl/fw_ram.v
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@ -30,45 +30,50 @@ module fw_ram(
//---------------------------------------------------------------- //----------------------------------------------------------------
// Registers and wires. // Registers and wires.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg [31 : 0] tmp_read_data;
reg [31 : 0] mem_read_data;
reg ready_reg; reg ready_reg;
reg fw_app_cs;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Concurrent assignment of ports. // Concurrent assignment of ports.
//---------------------------------------------------------------- //----------------------------------------------------------------
assign read_data = tmp_read_data;
assign ready = ready_reg; assign ready = ready_reg;
assign fw_app_cs = cs && ~fw_app_mode;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Block RAM instances. // Block RAM instances.
//---------------------------------------------------------------- //----------------------------------------------------------------
SB_RAM40_4K fw_ram0( SB_RAM40_4K fw_ram0(
.RDATA(read_data[15:0]), .RDATA(mem_read_data[15 : 0]),
.RADDR(address), .RADDR(address),
.RCLK(clk), .RCLK(clk),
.RCLKE(1'h1), .RCLKE(1'h1),
.RE(cs), .RE(fw_app_cs),
.WADDR(address), .WADDR(address),
.WCLK(clk), .WCLK(clk),
.WCLKE(1'h1), .WCLKE(1'h1),
.WDATA(write_data[15:0]), .WDATA(write_data[15 : 0]),
.WE(|we), .WE((|we && fw_app_cs)),
.MASK({{8{we[1]}}, {8{we[0]}}}) .MASK({{8{~we[1]}}, {8{~we[0]}}})
); );
SB_RAM40_4K fw_ram1( SB_RAM40_4K fw_ram1(
.RDATA(read_data[31:16]), .RDATA(mem_read_data[31 : 16]),
.RADDR(address), .RADDR(address),
.RCLK(clk), .RCLK(clk),
.RCLKE(1'h1), .RCLKE(1'h1),
.RE(cs), .RE(fw_app_cs),
.WADDR(address), .WADDR(address),
.WCLK(clk), .WCLK(clk),
.WCLKE(1'h1), .WCLKE(1'h1),
.WDATA(write_data[31:16]), .WDATA(write_data[31 : 16]),
.WE(|we), .WE((|we && fw_app_cs)),
.MASK({{8{we[3]}}, {8{we[2]}}}) .MASK({{8{~we[3]}}, {8{~we[2]}}})
); );
@ -85,6 +90,19 @@ module fw_ram(
end end
end end
//----------------------------------------------------------------
// read_mux
//----------------------------------------------------------------
always @*
begin : read_mux;
if (fw_app_cs) begin
tmp_read_data = mem_read_data;
end else begin
tmp_read_data = 32'h0;
end
end
endmodule // fw_ram endmodule // fw_ram
//====================================================================== //======================================================================