Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2024-12-20 21:34:28 -05:00
Code Issues Packages Projects Releases Wiki Activity

Move force_jump function to top level mem system

Browse Source 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2023-02-20 15:20:17 +01:00 committed by Daniel Lublin
parent 86ea45e10a
commit 8ba97e16f3
No known key found for this signature in database
GPG Key ID: 75BD0FEB8D3E7830
2 changed files with 70 additions and 75 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

135
hw/application_fpga/rtl/application_fpga.v
View File

@ -207,9 +207,6 @@ module application_fpga(
rom rom_inst( rom rom_inst(
.force_jump(force_jump),
.jump_instr(jump_instr),
.cs(rom_cs), .cs(rom_cs),
.address(rom_address), .address(rom_address),
.read_data(rom_read_data), .read_data(rom_read_data),
@ -418,80 +415,86 @@ module application_fpga(
tk1_write_data = cpu_wdata; tk1_write_data = cpu_wdata;
if (cpu_valid && !muxed_ready_reg) begin if (cpu_valid && !muxed_ready_reg) begin
case (area_prefix) if (force_jump) begin
ROM_PREFIX: begin muxed_rdata_new = jump_instr;
rom_cs = 1'h1; muxed_ready_new = 1'h1;
muxed_rdata_new = rom_read_data; end
muxed_ready_new = rom_ready; else begin
end case (area_prefix)
ROM_PREFIX: begin
rom_cs = 1'h1;
muxed_rdata_new = rom_read_data;
muxed_ready_new = rom_ready;
end
RAM_PREFIX: begin RAM_PREFIX: begin
ram_cs = 1'h1; ram_cs = 1'h1;
muxed_rdata_new = ram_read_data; muxed_rdata_new = ram_read_data;
muxed_ready_new = ram_ready; muxed_ready_new = ram_ready;
end end
RESERVED_PREFIX: begin RESERVED_PREFIX: begin
muxed_rdata_new = 32'h0; muxed_rdata_new = 32'h0;
muxed_ready_new = 1'h1; muxed_ready_new = 1'h1;
end end
MMIO_PREFIX: begin MMIO_PREFIX: begin
case (core_prefix) case (core_prefix)
TRNG_PREFIX: begin TRNG_PREFIX: begin
trng_cs = 1'h1; trng_cs = 1'h1;
muxed_rdata_new = trng_read_data; muxed_rdata_new = trng_read_data;
muxed_ready_new = trng_ready; muxed_ready_new = trng_ready;
end end
TIMER_PREFIX: begin TIMER_PREFIX: begin
timer_cs = 1'h1; timer_cs = 1'h1;
muxed_rdata_new = timer_read_data; muxed_rdata_new = timer_read_data;
muxed_ready_new = timer_ready; muxed_ready_new = timer_ready;
end end
UDS_PREFIX: begin UDS_PREFIX: begin
uds_cs = 1'h1; uds_cs = 1'h1;
muxed_rdata_new = uds_read_data; muxed_rdata_new = uds_read_data;
muxed_ready_new = uds_ready; muxed_ready_new = uds_ready;
end end
UART_PREFIX: begin UART_PREFIX: begin
uart_cs = 1'h1; uart_cs = 1'h1;
muxed_rdata_new = uart_read_data; muxed_rdata_new = uart_read_data;
muxed_ready_new = uart_ready; muxed_ready_new = uart_ready;
end end
TOUCH_SENSE_PREFIX: begin TOUCH_SENSE_PREFIX: begin
touch_sense_cs = 1'h1; touch_sense_cs = 1'h1;
muxed_rdata_new = touch_sense_read_data; muxed_rdata_new = touch_sense_read_data;
muxed_ready_new = touch_sense_ready; muxed_ready_new = touch_sense_ready;
end end
FW_RAM_PREFIX: begin FW_RAM_PREFIX: begin
fw_ram_cs = 1'h1; fw_ram_cs = 1'h1;
muxed_rdata_new = fw_ram_read_data; muxed_rdata_new = fw_ram_read_data;
muxed_ready_new = fw_ram_ready; muxed_ready_new = fw_ram_ready;
end end
TK1_PREFIX: begin TK1_PREFIX: begin
tk1_cs = 1'h1; tk1_cs = 1'h1;
muxed_rdata_new = tk1_read_data; muxed_rdata_new = tk1_read_data;
muxed_ready_new = tk1_ready; muxed_ready_new = tk1_ready;
end end
default: begin default: begin
muxed_rdata_new = 32'h0; muxed_rdata_new = 32'h0;
muxed_ready_new = 1'h1; muxed_ready_new = 1'h1;
end end
endcase // case (core_prefix) endcase // case (core_prefix)
end // case: MMIO_PREFIX end // case: MMIO_PREFIX
default: begin default: begin
muxed_rdata_new = 32'h0; muxed_rdata_new = 32'h0;
muxed_ready_new = 1'h1; muxed_ready_new = 1'h1;
end end
endcase // case (area_prefix) endcase // case (area_prefix)
end
end end
end end
endmodule // application_fpga endmodule // application_fpga

10
hw/application_fpga/rtl/rom.v
View File

@ -15,9 +15,6 @@
`default_nettype none `default_nettype none
module rom( module rom(
input wire force_jump,
input wire [31 : 0] jump_instr,
input wire cs, input wire cs,
/* verilator lint_off UNUSED */ /* verilator lint_off UNUSED */
input wire [11 : 0] address, input wire [11 : 0] address,
@ -63,12 +60,7 @@ module rom(
begin : rom_logic begin : rom_logic
/* verilator lint_off WIDTH */ /* verilator lint_off WIDTH */
if (force_jump) begin rom_rdata = memory[address];
rom_rdata = jump_instr;
end
else begin
rom_rdata = memory[address];
end
/* verilator lint_on WIDTH */ /* verilator lint_on WIDTH */
rom_ready = cs; rom_ready = cs;
end end