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Move force_jump function to top level mem system

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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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Joachim Strömbergson 2023-02-20 15:20:17 +01:00 • committed by Daniel Lublin
parent 86ea45e10a
commit 8ba97e16f3
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GPG key ID: 75BD0FEB8D3E7830
2 changed files with 70 additions and 75 deletions
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9
hw/application_fpga/rtl/application_fpga.v
View file

@ -207,9 +207,6 @@ module application_fpga(
rom rom_inst( rom rom_inst(
.force_jump(force_jump),
.jump_instr(jump_instr),
.cs(rom_cs), .cs(rom_cs),
.address(rom_address), .address(rom_address),
.read_data(rom_read_data), .read_data(rom_read_data),
@ -418,6 +415,11 @@ module application_fpga(
tk1_write_data = cpu_wdata; tk1_write_data = cpu_wdata;
if (cpu_valid && !muxed_ready_reg) begin if (cpu_valid && !muxed_ready_reg) begin
if (force_jump) begin
muxed_rdata_new = jump_instr;
muxed_ready_new = 1'h1;
end
else begin
case (area_prefix) case (area_prefix)
ROM_PREFIX: begin ROM_PREFIX: begin
rom_cs = 1'h1; rom_cs = 1'h1;
@ -494,6 +496,7 @@ module application_fpga(
endcase // case (area_prefix) endcase // case (area_prefix)
end end
end end
end
endmodule // application_fpga endmodule // application_fpga
//====================================================================== //======================================================================

8
hw/application_fpga/rtl/rom.v
View file

@ -15,9 +15,6 @@
`default_nettype none `default_nettype none
module rom( module rom(
input wire force_jump,
input wire [31 : 0] jump_instr,
input wire cs, input wire cs,
/* verilator lint_off UNUSED */ /* verilator lint_off UNUSED */
input wire [11 : 0] address, input wire [11 : 0] address,
@ -63,12 +60,7 @@ module rom(
begin : rom_logic begin : rom_logic
/* verilator lint_off WIDTH */ /* verilator lint_off WIDTH */
if (force_jump) begin
rom_rdata = jump_instr;
end
else begin
rom_rdata = memory[address]; rom_rdata = memory[address];
end
/* verilator lint_on WIDTH */ /* verilator lint_on WIDTH */
rom_ready = cs; rom_ready = cs;
end end